Koenemann; Bernd K. F.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Koenemann; Bernd K. F..The latest application filed is for "arrangement for testing semiconductor chips while incorporated on a semiconductor wafer".
- Koenemann; Bernd K. F. - San Jose CA
- Koenemann; Bernd K. F. - Hopewell Junction NY
| Patent | Date |
|---|---|
| Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer Grant 7,435,990 - Keller , et al. October 14, 2 | 2008-10-14 |
| Arrangement for testing semiconductor chips while incorporated on a semiconductor wafer App 20060284174 - Keller; Brion L. ; et al. | 2006-12-21 |
| Method And Apparatus For Compact Scan Testing App 20040139377 - Barnhart, Carl F. ; et al. | 2004-07-15 |
| An Arrangement For Testing Semiconductor Chips While Incorporated On A Semiconductor Wafer App 20040135231 - Keller, Brion L. ; et al. | 2004-07-15 |
| Hybrid pattern self-testing of integrated circuits Grant 5,612,963 - Koenemann , et al. March 18, 1 | 1997-03-18 |
| Method and apparatus for memory dynamic burn-in and test Grant 5,375,091 - Berry, Jr. , et al. December 20, 1 | 1994-12-20 |
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