Koehl; Juergen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Koehl; Juergen.The latest application filed is for "instruction scheduling approach to improve processor performance".

Company Profile

0.44.40

Koehl; Juergen - Boeblingen DE
Koehl; Juergen - Schoenbuch DE
Koehl; Juergen - Nuremberg N/A DE
Koehl; Juergen - Weil im Schoenbuch N/A DE
Koehl; Juergen - Weil Schoenbuch DE
Koehl; Juergen - Numberg DE
Koehl; Juergen - Well un Schoenbuch DE
Koehl; Juergen - Wei im Schoenbuch DE
Koehl; Juergen - Weil in Schoenbuch DE
Koehl; Juergen - D-71093 Weil im Schoenbuch DE
Koehl; Juergen - Weil i.Schoenbuch DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Instruction scheduling approach to improve processor performance Grant 9,256,430 - Koehl , et al. February 9, 2	2016-02-09
Instruction Scheduling Approach To Improve Processor Performance App 20150127926 - KOEHL; Juergen ; et al.	2015-05-07
Instruction scheduling approach to improve processor performance Grant 8,972,961 - Koehl , et al. March 3, 2	2015-03-03
Instruction scheduling approach to improve processor performance Grant 8,935,685 - Koehl , et al. January 13, 2	2015-01-13
Circuit macro placement using macro aspect ratio based on ports Grant 8,762,919 - Keinert , et al. June 24, 2	2014-06-24
Method and data processing system to optimize performance of an electric circuit design, data processing program and computer program product Grant 8,522,187 - Fricke , et al. August 27, 2	2013-08-27
Signal repowering chip for 3-dimensional integrated circuit Grant 8,513,663 - Buehler , et al. August 20, 2	2013-08-20
Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool Grant 8,418,090 - Bickford , et al. April 9, 2	2013-04-09
Instruction Scheduling Approach To Improve Processor Performance App 20120216016 - Koehl; Juergen ; et al.	2012-08-23
Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same Grant 8,234,594 - Anderson , et al. July 31, 2	2012-07-31
Method And Data Processing System To Optimize Performance Of An Electric Circuit Design, Data Processing Program And Computer Program Product App 20120144362 - Fricke; Niels ; et al.	2012-06-07
Method For Computing The Sensitivity Of A Vlsi Design To Both Random And Systematic Defects Using A Critical Area Analysis Tool App 20120137262 - Bickford; Jeanne P. ; et al.	2012-05-31
Apparatus and computer program product for semiconductor yield estimation Grant 8,136,066 - Bickford , et al. March 13, 2	2012-03-13
Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool Grant 8,132,129 - Bickford , et al. March 6, 2	2012-03-06
Instruction Scheduling Approach To Improve Processor Performance App 20110289297 - Koehl; Juergen ; et al.	2011-11-24
Circuit Macro Placement Using Macro Aspect Ratio Based on Ports App 20110289468 - Keinert; Joachim ; et al.	2011-11-24
Method for validating logical function and timing behavior of a digital circuit decision Grant 8,056,037 - Koehl , et al. November 8, 2	2011-11-08
Routing of wires of an electronic circuit Grant 8,015,527 - Buehler , et al. September 6, 2	2011-09-06
Method and system for placement of electric circuit components in integrated circuit design Grant 8,010,925 - Buehler , et al. August 30, 2	2011-08-30
Test yield estimate for semiconductor products created from a library Grant 8,010,916 - Bickford , et al. August 30, 2	2011-08-30
Computer readable medium, system and associated method for designing integrated circuits with loop insertions Grant 7,996,808 - Arp , et al. August 9, 2	2011-08-09
Design structure for a redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same Grant 7,984,394 - Anderson , et al. July 19, 2	2011-07-19
Redundant micro-loop structure for use in an integrated circuit physical design process and method of forming the same Grant 7,960,836 - Anderson , et al. June 14, 2	2011-06-14
Via structure to improve routing of wires within an integrated circuit Grant 7,962,881 - Buehler , et al. June 14, 2	2011-06-14
Method and apparatus for manufacturing diamond shaped chips Grant 7,961,932 - Allen , et al. June 14, 2	2011-06-14
Port assignment in hierarchical designs by abstracting macro logic Grant 7,962,877 - Keinert , et al. June 14, 2	2011-06-14
Structure for optimizing the signal time behavior of an electronic circuit design Grant 7,886,245 - Hutzl , et al. February 8, 2	2011-02-08
Method and system for generating a layout for an integrated electronic circuit Grant 7,865,855 - Koehl , et al. January 4, 2	2011-01-04
Method and computer system for optimizing the signal time behavior of an electronic circuit design Grant 7,844,931 - Hutzl , et al. November 30, 2	2010-11-30
Post-routing Coupling Fixes For Integrated Circuits App 20100257503 - Buehler; Markus ; et al.	2010-10-07
Signal Repowering Chip For 3-Dimensional Integrated Circuit App 20100237700 - Buehler; Markus ; et al.	2010-09-23
Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same App 20100211923 - Anderson; Brent A. ; et al.	2010-08-19
Redundancy in signal distribution trees Grant 7,755,408 - Ehrenreich , et al. July 13, 2	2010-07-13
Port Assignment In Hierarchical Designs By Abstracting Macro Logic App 20100037198 - Keinert; Joachim ; et al.	2010-02-11
Via Structure To Improve Routing Of Wires Within An Integrated Circuit App 20100031220 - Buehler; Markus T. ; et al.	2010-02-04
Design Structure for a Redundant Micro-Loop Structure for use in an Integrated Circuit Physical Design Process and Method of Forming the Same App 20090158231 - Anderson; Brent A. ; et al.	2009-06-18
Apparatus And Computer Program Product For Semiconductor Yield Estimation App 20090113364 - Bickford; Jeanne Paulette Spence ; et al.	2009-04-30
Method For Computing The Sensistivity Of A Vlsi Design To Both Random And Systematic Defects Using A Critical Area Analysis Tool App 20090113360 - BICKFORD; JEANNE P. ; et al.	2009-04-30
Method for routing data paths in a semiconductor chip with a plurality of layers Grant 7,526,743 - Arp , et al. April 28, 2	2009-04-28
Method for Violating the Logical Function and Timing Behavior of a Digital Circuit Decision App 20090083684 - Koehl; Juergen ; et al.	2009-03-26
Method And System For Generating A Layout For An Integrated Electronic Circuit App 20090064069 - Koehl; Juergen ; et al.	2009-03-05
Semiconductor yield estimation Grant 7,496,874 - Bickford , et al. February 24, 2	2009-02-24
Method for creating a layout for an electronic circuit Grant 7,490,310 - Koehl , et al. February 10, 2	2009-02-10
Method for computing the sensitivity of a VLSI design to both random and systematic defects using a critical area analysis tool Grant 7,487,476 - Bickford , et al. February 3, 2	2009-02-03
Computer Readable Medium, System and Associated Method For Designing Integrated Circuits With Loop Insertions App 20090031274 - Arp; Andreas ; et al.	2009-01-29
Delay Calculation Method, A Data Processing Program and A Computer Program Product for Routing of Wires of an Electronic Circuit App 20090013293 - Buehler; Markus ; et al.	2009-01-08
Method and System for Placement of Electric Circuit Components in Integrated Circuit Design App 20080301612 - Buehler; Markus ; et al.	2008-12-04
Redundancy in Signal Distribution Trees App 20080256413 - Ehrenreich; Sebastian ; et al.	2008-10-16
Structure for Optimizing the Signal Time Behavior of an Electronic Circuit Design App 20080216043 - Hutzl; Guenther ; et al.	2008-09-04
Method and Computer System for Otimizing the Signal Time Behavior of an Electronic Circuit Design App 20080216042 - Hutzl; Guenther ; et al.	2008-09-04
Test Yield Estimate For Semiconductor Products Created From A Library App 20080189664 - Bickford; Jeanne ; et al.	2008-08-07
Yield optimization in router for systematic defects Grant 7,398,485 - Bickford , et al. July 8, 2	2008-07-08
Redundant Micro-loop Structure For Use In An Intergrated Circuit Physical Design Process And Method Of Forming The Same App 20080150149 - Anderson; Brent A. ; et al.	2008-06-26
Regular routing for deep sub-micron chip design Grant 7,392,497 - Fassnacht , et al. June 24, 2	2008-06-24
Test yield estimate for semiconductor products created from a library Grant 7,386,815 - Bickford , et al. June 10, 2	2008-06-10
Redundant Micro-Loop Structure For Use In An Integrated Circuit Physical Design Process And Method Of Forming The Same App 20080097738 - Anderson; Brent A. ; et al.	2008-04-24
Method and System for Designing Fan-out Nets Connecting a Signal Source and Plurality of Active Net Elements in an Integrated Circuit App 20080059933 - Barke; Erich ; et al.	2008-03-06
Redundancy in signal distribution trees Grant 7,336,115 - Ehrenreich , et al. February 26, 2	2008-02-26
Method And Apparatus For Manufacturing Diamond Shaped Chips App 20080018872 - Allen; Robert J. ; et al.	2008-01-24
Use of redundant routes to increase the yield and reliability of a VLSI layout Grant 7,308,669 - Buehler , et al. December 11, 2	2007-12-11
Method and apparatus for manufacturing diamond shaped chips Grant 7,289,659 - Allen , et al. October 30, 2	2007-10-30
Method For Computing The Sensitivity Of A Vlsi Design To Both Random And Systematic Defects Using A Critical Area Analysis Tool App 20070240085 - Bickford; Jeanne P. ; et al.	2007-10-11
Yield Optimization In Router For Systematic Defects App 20070240090 - Bickford; JeanneP ; et al.	2007-10-11
A Method , Apparatus And Computer Program Product For Semiconductor Yield Estimation App 20070143720 - Bickford; Jeanne Paulette Spence ; et al.	2007-06-21
Test Yield Estimate For Semiconductor Products Created From A Library App 20070099236 - Bickford; Jeanne ; et al.	2007-05-03
Method and Tool for Creating a Layout for an Electronic Circuit App 20070089079 - Koehl; Juergen ; et al.	2007-04-19
Method of providing a non-blocking routing network Grant 7,206,308 - Koehl , et al. April 17, 2	2007-04-17
Switching arrangement and method with separated output buffers Grant 7,145,873 - Luijten , et al. December 5, 2	2006-12-05
The Use Of Redundant Routes To Increase The Yield And Reliability Of A Vlsi Layout App 20060265684 - Buehler; Markus T. ; et al.	2006-11-23
Redundancy in signal distribution trees App 20060179396 - Ehrenreich; Sebastian ; et al.	2006-08-10
Method For Routing Data Paths In A Semiconductor Chip With A Plurality Of Layers App 20060044932 - Arp; Andreas ; et al.	2006-03-02
Regular Routing For Deep Submicron Chip Design App 20060031805 - Fassnacht; Uwe ; et al.	2006-02-09
Method and system for placing logic nodes based on an estimated wiring congestion Grant 6,904,584 - Brenner , et al. June 7, 2	2005-06-07
Method And Apparatus For Manufacturing Diamond Shaped Chips App 20040258294 - Allen, Robert J. ; et al.	2004-12-23
Method and system for placing logic nodes based on an estimated wiring congestion App 20030208737 - Brenner, Ulrich ; et al.	2003-11-06
Method of providing a non-blocking routing network App 20030117947 - Koehl, Juergen ; et al.	2003-06-26
Switching arrangement and method with separated output buffers App 20020118689 - Luijten, Ronald P. ; et al.	2002-08-29
Structure for reducing cross-talk in VLSI circuits and method of making same using filled channels to minimize cross-talk Grant 6,218,631 - Hetzel , et al. April 17, 2	2001-04-17

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.