loadpatents
name:-0.0092411041259766
name:-0.0058338642120361
name:-0.0013720989227295
Koebernik; Gert Patent Filings

Koebernik; Gert

Patent Applications and Registrations

Patent applications and USPTO patent grants for Koebernik; Gert.The latest application filed is for "integrated circuits having a controller to control a read operation and methods for operating the same".

Company Profile
0.5.6
  • Koebernik; Gert - Unterhaching DE
  • Koebernik; Gert - Munic DE
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Integrated circuits and methods for operating the same using a plurality of buffer circuits in an access operation
Grant 7,920,430 - Koebernik , et al. April 5, 2
2011-04-05
Integrated circuits having a controller to control a read operation and methods for operating the same
Grant 7,864,579 - Gutsche , et al. January 4, 2
2011-01-04
Integrated circuit having a memory cell arrangement and method for reading a memory cell state using a plurality of partial readings
Grant 7,800,943 - Ravasio , et al. September 21, 2
2010-09-21
Integrated circuit, method to program a memory cell array of an integrated circuit, and memory module
Grant 7,796,449 - Willer , et al. September 14, 2
2010-09-14
Integrated Circuits Having a Controller to Control a Read Operation and Methods for Operating the Same
App 20100020610 - Gutsche; Jan ;   et al.
2010-01-28
Integrated circuits; methods for manufacturing an integrated circuit; memory modules; computing systems
Grant 7,649,779 - Ruttkowski , et al. January 19, 2
2010-01-19
Integrated Circuits and Methods for Operating the Same Using a Plurality of Buffer Circuits in an Access Operation
App 20100002503 - Koebernik; Gert ;   et al.
2010-01-07
Integrated Circuit, Method To Program A Memory Cell Array Of An Integrated Circuit, And Memory Module
App 20090201740 - WILLER; Josef ;   et al.
2009-08-13
Integrated Circuit Having a Memory Cell Arrangement and Method for Reading a Memory Cell State Using a Plurality of Partial Readings
App 20090185425 - Ravasio; Roberto ;   et al.
2009-07-23
Integrated Circuits; Methods for Manufacturing an Integrated Circuit; Memory Modules; Computing Systems
App 20080285344 - Ruttkowski; Eike ;   et al.
2008-11-20
Method for setting a read voltage, and semiconductor circuit arrangement
App 20080002452 - Augustin; Uwe ;   et al.
2008-01-03

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed