Kodalapura; Nagaraju N.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Kodalapura; Nagaraju N..The latest application filed is for "techniques for preventing memory timing attacks".
- Kodalapura; Nagaraju N. - Hillsboro OR
- Kodalapura, Nagaraju N. - Bangalore IN
| Patent | Date |
|---|---|
| Techniques For Preventing Memory Timing Attacks App 20210351911 - Kodalapura; Nagaraju N. ; et al. | 2021-11-11 |
| Hardware based technique to prevent critical fine-grained cache side-channel attacks Grant 11,144,468 - Basak , et al. October 12, 2 | 2021-10-12 |
| Techniques for preventing memory timing attacks Grant 11,121,853 - Kodalapura , et al. September 14, 2 | 2021-09-14 |
| Mapping security policy group registers Grant 10,318,440 - Kodalapura , et al. | 2019-06-11 |
| Techniques For Preventing Memory Timing Attacks App 20190132115 - Kodalapura; Nagaraju N. ; et al. | 2019-05-02 |
| Hardware Based Technique To Prevent Critical Fine-grained Cache Side-channel Attacks App 20190042453 - Basak; Abhishek ; et al. | 2019-02-07 |
| Techniques for preventing memory timing attacks Grant 10,116,436 - Kodalapura , et al. October 30, 2 | 2018-10-30 |
| Mapping Security Policy Group Registers App 20180091554 - Kodalapura; Nagaraju N. ; et al. | 2018-03-29 |
| Combined emulation and simulation debugging techniques App 20050071812 - Ramkumar, Peramachanahalli S. ; et al. | 2005-03-31 |
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