loadpatents
name:-0.017198085784912
name:-0.012109994888306
name:-0.0028140544891357
Kocian; Thomas Allan Patent Filings

Kocian; Thomas Allan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kocian; Thomas Allan.The latest application filed is for "wafer level mems package including dual seal ring".

Company Profile
1.10.12
  • Kocian; Thomas Allan - Dallas TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Wafer level MEMS package including dual seal ring
Grant 9,969,610 - Diep , et al. May 15, 2
2018-05-15
Wafer level MEMS package including dual seal ring
Grant 9,771,258 - Diep , et al. September 26, 2
2017-09-26
Hermetically sealed package having stress reducing layer
Grant 9,708,181 - Kennedy , et al. July 18, 2
2017-07-18
Wafer Level Mems Package Including Dual Seal Ring
App 20170129775 - Diep; Buu Q. ;   et al.
2017-05-11
Wafer Level Mems Package Including Dual Seal Ring
App 20160376146 - Diep; Buu Q. ;   et al.
2016-12-29
Hermetically Sealed Package Having Stress Reducing Layer
App 20160167959 - Kennedy; Adam M. ;   et al.
2016-06-16
Hermetically sealed package having stress reducing layer
Grant 9,334,154 - Kennedy , et al. May 10, 2
2016-05-10
Getter Structure And Method For Forming Such Structure
App 20160040282 - Gooch; Roland ;   et al.
2016-02-11
Hermetically Sealed Package Having Stress Reducing Layer
App 20160039665 - Kennedy; Adam M. ;   et al.
2016-02-11
Getter structure and method for forming such structure
Grant 9,196,556 - Gooch , et al. November 24, 2
2015-11-24
Integrated bondline spacers for wafer level packaged circuit devices
Grant 9,187,312 - Gooch , et al. November 17, 2
2015-11-17
Integrated bondline spacers for wafer level packaged circuit devices
Grant 9,174,836 - Gooch , et al. November 3, 2
2015-11-03
Getter Structure And Method For Forming Such Structure
App 20150249042 - Gooch; Roland ;   et al.
2015-09-03
Method of forming deposited patterns on a surface
Grant 9,105,800 - Gooch , et al. August 11, 2
2015-08-11
Wafer level package solder barrier used as vacuum getter
Grant 9,093,444 - Gooch , et al. July 28, 2
2015-07-28
Method Of Forming Deposited Patterns On A Surface
App 20150162479 - Gooch; Roland ;   et al.
2015-06-11
Wafer Level Package Solder Barrier Used As Vacuum Getter
App 20150014854 - Gooch; Roland W. ;   et al.
2015-01-15
Integrated Bondline Spacers For Wafer Level Packaged Circuit Devices
App 20140346643 - Gooch; Roland ;   et al.
2014-11-27
Integrated Bondline Spacers For Wafer Level Packaged Circuit Devices
App 20140193948 - Gooch; Roland ;   et al.
2014-07-10
Getter Structure For Wafer Level Vacuum Packaged Device
App 20140175590 - Gooch; Roland ;   et al.
2014-06-26
Integrated bondline spacers for wafer level packaged circuit devices
Grant 8,736,045 - Gooch , et al. May 27, 2
2014-05-27
Integrated Bondline Spacers For Wafer Level Packaged Circuit Devices
App 20140124899 - Gooch; Roland ;   et al.
2014-05-08

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