Koburger, III; Charles William

Patent Applications and Registrations

Patent applications and USPTO patent grants for Koburger, III; Charles William.The latest application filed is for "self-aligned dielectric isolation for finfet devices".

Company Profile

0.71.9

Koburger, III; Charles William - Delmar NY
Koburger, III; Charles William - Albany NY
Koburger, III; Charles William - Essex Junction VT

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Self-aligned dielectric isolation for FinFET devices Grant 9,627,377 - Bergendahl , et al. April 18, 2	2017-04-18
Self-aligned Dielectric Isolation For Finfet Devices App 20150061040 - Bergendahl; Marc Adam ; et al.	2015-03-05
Self-aligned dielectric isolation for FinFET devices Grant 8,941,156 - Bergendahl , et al. January 27, 2	2015-01-27
Method of forming finFET of variable channel width Grant 8,896,067 - Bergendahl , et al. November 25, 2	2014-11-25
Self-aligned Dielectric Isolation For Finfet Devices App 20140191296 - Bergendahl; Marc Adam ; et al.	2014-07-10
Method Of Forming Finfet Of Variable Channel Width App 20140191323 - Bergendahl; Marc Adam ; et al.	2014-07-10
Field-effect-transistor with self-aligned diffusion contact Grant 8,637,358 - Koburger, III , et al. January 28, 2	2014-01-28
Field-effect-transistor With Self-aligned Diffusion Contact App 20140008731 - Koburger, III; Charles William ; et al.	2014-01-09
Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby Grant 8,450,806 - Furukawa , et al. May 28, 2	2013-05-28
Metal-oxide-semiconductor device structures with tailored dopant depth profiles Grant 7,994,575 - Furukawa , et al. August 9, 2	2011-08-09
Method of making integrated circuit chip utilizing oriented carbon nanotube conductive layers Grant 7,989,222 - Furukawa , et al. August 2, 2	2011-08-02
Semiconductor transistors with contact holes close to gates Grant 7,985,643 - Furukawa , et al. July 26, 2	2011-07-26
Methods for fabricating a metal-oxide-semiconductor device structure Grant 7,951,660 - Furukawa , et al. May 31, 2	2011-05-31
Phase change memory cell with vertical transistor Grant 7,932,167 - Furukawa , et al. April 26, 2	2011-04-26
Layer patterning using double exposure processes in a single photoresist layer Grant 7,923,202 - Furukawa , et al. April 12, 2	2011-04-12
Passive electrically testable acceleration and voltage measurement devices Grant 7,898,045 - Furukawa , et al. March 1, 2	2011-03-01
Semiconductor Device With Enhanced Stress By Gates Stress Liner App 20110042728 - Cheng; Kangguo ; et al.	2011-02-24
Methods and structures for promoting stable synthesis of carbon nanotubes Grant 7,851,064 - Furukawa , et al. December 14, 2	2010-12-14
Vertical carbon nanotube field effect transistors and arrays Grant 7,829,883 - Furukawa , et al. November 9, 2	2010-11-09
Layout and process to contact sub-lithographic structures Grant 7,825,525 - Furukawa , et al. November 2, 2	2010-11-02
Method of Making Integrated Circuit Chip Utilizing Oriented Carbon Nanotube Conductive Layers App 20100273298 - Furukawa; Toshiharu ; et al.	2010-10-28
Methods of fabricating vertical carbon nanotube field effect transistors for arrangement in arrays and field effect transistors and arrays formed thereby Grant 7,820,502 - Furukawa , et al. October 26, 2	2010-10-26
Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures Grant 7,791,145 - Furukawa , et al. September 7, 2	2010-09-07
Integrated circuit chip utilizing oriented carbon nanotube conductive layers Grant 7,786,583 - Furukawa , et al. August 31, 2	2010-08-31
Design structure incorporating a hybrid substrate Grant 7,750,406 - Cannon , et al. July 6, 2	2010-07-06
Well isolation trenches (WIT) for CMOS devices Grant 7,737,504 - Furukawa , et al. June 15, 2	2010-06-15
Methods and semiconductor structures for latch-up suppression using a conductive region Grant 7,727,848 - Furukawa , et al. June 1, 2	2010-06-01
Method for fabricating strained silicon-on-insulator structures and strained silicon-on-insulator structures formed thereby Grant 7,704,855 - Furukawa , et al. April 27, 2	2010-04-27
Sidewall image transfer processes for forming multiple line-widths Grant 7,699,996 - Furukawa , et al. April 20, 2	2010-04-20
Vertical nanotube semiconductor device structures and methods of forming the same Grant 7,691,720 - Furukawa , et al. April 6, 2	2010-04-06
Method of forming a dual gated FinFET gain cell Grant 7,674,674 - Furukawa , et al. March 9, 2	2010-03-09
Non-volatile switching and memory devices using vertical nanotubes Grant 7,668,004 - Furukawa , et al. February 23, 2	2010-02-23
Methods and semiconductor structures for latch-up suppression using a conductive region Grant 7,655,985 - Furukawa , et al. February 2, 2	2010-02-02
Hybrid substrates and methods for forming such hybrid substrates Grant 7,651,902 - Cannon , et al. January 26, 2	2010-01-26
Method of fabricating semiconductor structures for latch-up suppression Grant 7,648,869 - Chang , et al. January 19, 2	2010-01-19
Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures Grant 7,645,676 - Furukawa , et al. January 12, 2	2010-01-12
Passive electrically testable acceleration and voltage measurement devices Grant 7,629,192 - Furukawa , et al. December 8, 2	2009-12-08
Micro-electro-mechanical valves and pumps and methods of fabricating same Grant 7,607,455 - Furukawa , et al. October 27, 2	2009-10-27
Methods of forming low-k dielectric layers containing carbon nanostructures Grant 7,579,272 - Furukawa , et al. August 25, 2	2009-08-25
Method of forming a dual gated FinFET gain cell Grant 7,566,613 - Furukawa , et al. July 28, 2	2009-07-28
Methods for forming a wrap-around gate field effect transistor Grant 7,560,347 - Furukawa , et al. July 14, 2	2009-07-14
Shallow trench isolation fill by liquid phase deposition of SiO.sub.2 Grant 7,525,156 - Hakey , et al. April 28, 2	2009-04-28
Method of forming optical sensor that includes three pairs of electrodes formed at different depths in a semiconductor substrate Grant 7,517,716 - Furukawa , et al. April 14, 2	2009-04-14
Micro-electro-mechanical valves and pumps Grant 7,505,110 - Furukawa , et al. March 17, 2	2009-03-17
Electric fuses using CNTs (carbon nanotubes) Grant 7,492,046 - Furukawa , et al. February 17, 2	2009-02-17
Methods and semiconductor structures for latch-up suppression using a conductive region Grant 7,491,618 - Furukawa , et al. February 17, 2	2009-02-17
Layer Patterning Using Double Exposure Processes In A Single Photoresist Layer App 20090035708 - Furukawa; Toshiharu ; et al.	2009-02-05
Memory devices using carbon nanotube (CNT) technologies Grant 7,483,285 - Furukawa , et al. January 27, 2	2009-01-27
Method for making integrated circuit chip having carbon nanotube composite interconnection vias Grant 7,473,633 - Furukawa , et al. January 6, 2	2009-01-06
Phase Change Memory Cell with Vertical Transistor App 20090001337 - Furukawa; Toshiharu ; et al.	2009-01-01
Method for making integrated circuit chip utilizing oriented carbon nanotube conductive layers Grant 7,439,081 - Furukawa , et al. October 21, 2	2008-10-21
Methods for forming a wrap-around gate field effect transistor Grant 7,435,653 - Furukawa , et al. October 14, 2	2008-10-14
High performance single event upset hardened SRAM cell Grant 7,397,692 - Cannon , et al. July 8, 2	2008-07-08
Memory devices using carbon nanotube (CNT) technologies Grant 7,385,839 - Furukawa , et al. June 10, 2	2008-06-10
Shallow trench isolation method for shielding trapped charge in a semiconductor device Grant 7,385,275 - Cannon , et al. June 10, 2	2008-06-10
Methods and structures for promoting stable synthesis of carbon nanotubes Grant 7,374,793 - Furukawa , et al. May 20, 2	2008-05-20
Layout and process to contact sub-lithographic structures Grant 7,351,666 - Furukawa , et al. April 1, 2	2008-04-01
Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures Grant 7,276,768 - Furukawa , et al. October 2, 2	2007-10-02
Shallow trench isolation fill by liquid phase deposition of SiO2 Grant 7,273,794 - Hakey , et al. September 25, 2	2007-09-25
Wrap-around gate field effect transistor Grant 7,271,444 - Furukawa , et al. September 18, 2	2007-09-18
Wafer cell for immersion lithography Grant 7,271,878 - Furukawa , et al. September 18, 2	2007-09-18
Well isolation trenches (WIT) for CMOS devices Grant 7,268,028 - Furukawa , et al. September 11, 2	2007-09-11
Methods of forming alternating phase shift masks having improved phase-shift tolerance Grant 7,264,415 - Furukawa , et al. September 4, 2	2007-09-04
Integrated circuit chip utilizing dielectric layer having oriented cylindrical voids formed from carbon nanotubes Grant 7,229,909 - Furukawa , et al. June 12, 2	2007-06-12
Integrated circuit chip utilizing carbon nanotube composite interconnection vias Grant 7,135,773 - Furukawa , et al. November 14, 2	2006-11-14
Integrated circuit chip utilizing oriented carbon nanotube conductive layers Grant 7,129,097 - Furukawa , et al. October 31, 2	2006-10-31
Horizontal memory gain cells Grant 7,109,546 - Furukawa , et al. September 19, 2	2006-09-19
Strained semiconductor device structures Grant 7,102,201 - Furukawa , et al. September 5, 2	2006-09-05
Moving lens for immersion optical lithography Grant 7,088,422 - Hakey , et al. August 8, 2	2006-08-08
Selective synthesis of semiconducting carbon nanotubes Grant 7,038,299 - Furukawa , et al. May 2, 2	2006-05-02
System and apparatus for photolithography Grant 7,027,125 - Hakey , et al. April 11, 2	2006-04-11
Method of forming FinFET gates without long etches Grant 6,989,308 - Furukawa , et al. January 24, 2	2006-01-24
Dual gated finfet gain cell Grant 6,970,372 - Furukawa , et al. November 29, 2	2005-11-29
Method for supporting a bond pad in a multilevel interconnect structure and support structure formed thereby Grant 6,890,828 - Horak , et al. May 10, 2	2005-05-10
Method for forming quadruple density sidewall image transfer (SIT) structures Grant 6,875,703 - Furukawa , et al. April 5, 2	2005-04-05
Method for manufacturing a multi-level interconnect structure Grant 6,713,835 - Horak , et al. March 30, 2	2004-03-30
Low-leakage borderless contacts to doped regions Grant 5,894,169 - Givens , et al. April 13, 1	1999-04-13

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