Koburger; Charles W.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Koburger; Charles W..The latest application filed is for "integrated circuit structure having selectively formed metal cap".

Company Profile

0.10.12

Koburger; Charles W. - Delmar NY
Koburger; Charles W - Delmar NY US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integrated circuit structure having selectively formed metal cap Grant 9,379,198 - Yang , et al. June 28, 2	2016-06-28
Silicon-on-insulator transistor with self-aligned borderless source/drain contacts Grant 9,368,590 - Fan , et al. June 14, 2	2016-06-14
Integrated Circuit Structure Having Selectively Formed Metal Cap App 20150008527 - Yang; Chih-Chao ; et al.	2015-01-08
Borderless contact structure employing dual etch stop layers Grant 8,796,783 - Fan , et al. August 5, 2	2014-08-05
Air-dielectric for subtractive etch line and via metallization Grant 8,735,279 - Horak , et al. May 27, 2	2014-05-27
Metal alloy cap integration Grant 8,716,127 - Yang , et al. May 6, 2	2014-05-06
Silicon-on-insulator Transistor With Self-aligned Borderless Source/drain Contacts App 20140061799 - FAN; Susan S. ; et al.	2014-03-06
Interconnect structures and methods for back end of the line integration Grant 8,637,400 - Horak , et al. January 28, 2	2014-01-28
Metal Alloy Cap Integration App 20130252419 - Yang; Chih-Chao ; et al.	2013-09-26
Borderless Contact Structure Employing Dual Etch Stop Layers App 20130168749 - Fan; Su C. ; et al.	2013-07-04
Memory device and method of manufacturing the device by simultaneously conditioning transition metal oxide layers in a plurality of memory cells Grant 7,541,608 - Furukawa , et al. June 2, 2	2009-06-02
Microelectronic structure by selective deposition Grant 7,510,939 - Furukawa , et al. March 31, 2	2009-03-31
Immersion optical lithography system having protective optical coating App 20080225251 - Holmes; Steven J. ; et al.	2008-09-18
Methods Of Forming Gas Dielectric And Related Structure App 20080217730 - Furukawa; Toshiharu ; et al.	2008-09-11
Mandrel/trim Alignment In Sit Processing App 20080188080 - Furukawa; Toshiharu ; et al.	2008-08-07
Simultaneous Conditioning of a Plurality of Memory Cells Through Series Resistors App 20080185652 - Furukawa; Toshijaru ; et al.	2008-08-07
Semiconductor Devices With Buried Isolation Regions App 20080128811 - Furukawa; Toshiharu ; et al.	2008-06-05
Memory Device And Mehtod Of Manufacturing The Device By Simulataneously Conditioning Transition Metal Oxide Layers In A Plurality Of Memory Cells App 20080131995 - Furukawa; Toshijaru ; et al.	2008-06-05
Illumination Light In Immersion Lithography Stepper For Particle Or Bubble Detection App 20070296937 - Furukawa; Toshiharu ; et al.	2007-12-27
Method And Structure For Forming Self-planarizing Wiring Layers In Multilevel Electronic Devices App 20070290394 - Furukawa; Toshiharu ; et al.	2007-12-20

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.