| Patent | Date |
|---|
Backside source/drain replacement for semiconductor devices with metallization on both sides
Grant 11,444,166 - Glass , et al. September 13, 2 | 2022-09-13 |
Deep Trench Via For Three-dimensional Integrated Circuit
App 20220285342 - WANG; Yih ; et al. | 2022-09-08 |
Gate-all-around Integrated Circuit Structures Having Asymmetric Source And Drain Contact Structures
App 20220262957 - GUHA; Biswajeet ; et al. | 2022-08-18 |
Transistor Cells Including A Deep Via Lined With A Dielectric Material
App 20220254681 - Morrow; Patrick ; et al. | 2022-08-11 |
Deep trench via for three-dimensional integrated circuit
Grant 11,373,999 - Wang , et al. June 28, 2 | 2022-06-28 |
Gate-all-around integrated circuit structures having asymmetric source and drain contact structures
Grant 11,367,796 - Guha , et al. June 21, 2 | 2022-06-21 |
Hybrid Manufacturing For Integrating Photonic And Electronic Components
App 20220187536 - Sharma; Abhishek A. ; et al. | 2022-06-16 |
Hybrid Manufacturing For Integrated Circuit Devices And Assemblies
App 20220181256 - Gomes; Wilfred ; et al. | 2022-06-09 |
Hybrid Manufacturing For Integrated Circuit Devices And Assemblies
App 20220181313 - Gomes; Wilfred ; et al. | 2022-06-09 |
Integrated Circuit Assemblies With Direct Chip Attach To Circuit Boards
App 20220173046 - Gomes; Wilfred ; et al. | 2022-06-02 |
Transistors with back-side contacts to create three dimensional memory and logic
Grant 11,335,686 - Gomes , et al. May 17, 2 | 2022-05-17 |
Transistor cells including a deep via lined wit h a dielectric material
Grant 11,328,951 - Morrow , et al. May 10, 2 | 2022-05-10 |
Integrated circuit structures having differentiated neighboring partitioned source or drain contact structures
Grant 11,329,162 - Kobrinsky , et al. May 10, 2 | 2022-05-10 |
Use Of A Placeholder For Backside Contact Formation For Transistor Arrangements
App 20220139911 - Wei; Andy Chih-Hung ; et al. | 2022-05-05 |
Three-dimensional Nanoribbon-based Dynamic Random-access Memory
App 20220068931 - Gomes; Wilfred ; et al. | 2022-03-03 |
Three-dimensional nanoribbon-based dynamic random-access memory
Grant 11,257,822 - Gomes , et al. February 22, 2 | 2022-02-22 |
Thin Film Transistor Based Memory Cells On Both Sides Of A Layer Of Logic Devices
App 20220045065 - Gomes; Wilfred ; et al. | 2022-02-10 |
Thin film transistor based memory cells on both sides of a layer of logic devices
Grant 11,239,238 - Gomes , et al. February 1, 2 | 2022-02-01 |
Integrated Circuit Device With Crenellated Metal Trace Layout
App 20220028779 - Morrow; Patrick ; et al. | 2022-01-27 |
Microelectronic Package With Three-dimensional (3d) Monolithic Memory Die
App 20210375849 - Gomes; Wilfred ; et al. | 2021-12-02 |
Three-dimensional Memory Arrays With Layer Selector Transistors
App 20210335791 - Gomes; Wilfred ; et al. | 2021-10-28 |
Integrated circuit device with crenellated metal trace layout
Grant 11,139,241 - Morrow , et al. October 5, 2 | 2021-10-05 |
Three-dimensional memory arrays with layer selector transistors
Grant 11,139,300 - Gomes , et al. October 5, 2 | 2021-10-05 |
Three-dimensional Nanoribbon-based Static Random-access Memory
App 20210272624 - Gomes; Wilfred ; et al. | 2021-09-02 |
Three-dimensional nanoribbon-based static random-access memory
Grant 11,087,832 - Gomes , et al. August 10, 2 | 2021-08-10 |
Interconnect fabricated with flowable copper
Grant 11,062,995 - Naylor , et al. July 13, 2 | 2021-07-13 |
Dense memory arrays utilizing access transistors with back-side contacts
Grant 11,056,492 - Gomes , et al. July 6, 2 | 2021-07-06 |
Fluid viscosity control during wafer bonding
Grant 11,056,356 - Mueller , et al. July 6, 2 | 2021-07-06 |
Dense Memory Arrays Utilizing Access Transistors With Back-side Contacts
App 20210193666 - Gomes; Wilfred ; et al. | 2021-06-24 |
Three-dimensional Nanoribbon-based Dynamic Random-access Memory
App 20210159229 - Gomes; Wilfred ; et al. | 2021-05-27 |
Three-dimensional Memory Arrays With Layer Selector Transistors
App 20210151438 - Gomes; Wilfred ; et al. | 2021-05-20 |
Transistors With Back-side Contacts To Create Three Dimensional Memory And Logic
App 20210134802 - Gomes; Wilfred ; et al. | 2021-05-06 |
Thin Film Transistor Based Memory Cells On Both Sides Of A Layer Of Logic Devices
App 20210125990 - Gomes; Wilfred ; et al. | 2021-04-29 |
Interconnect Fabricated With Flowable Copper
App 20210111129 - Naylor; Carl H. ; et al. | 2021-04-15 |
Integrated Circuit Device With Back-side Inerconnection To Deep Source/drain Semiconductor
App 20210111115 - Morrow; Patrick ; et al. | 2021-04-15 |
Backside Source/drain Replacement For Semiconductor Devices With Metallization On Both Sides
App 20210074823 - Glass; Glenn A. ; et al. | 2021-03-11 |
Backside source/drain replacement for semiconductor devices with metallization on both sides
Grant 10,892,337 - Glass , et al. January 12, 2 | 2021-01-12 |
Integrated circuit device with back-side interconnection to deep source/drain semiconductor
Grant 10,886,217 - Morrow , et al. January 5, 2 | 2021-01-05 |
Methods of forming backside self-aligned vias and structures formed thereby
Grant 10,797,139 - Morrow , et al. October 6, 2 | 2020-10-06 |
Backside contact resistance reduction for semiconductor devices with metallization on both sides
Grant 10,734,412 - Glass , et al. | 2020-08-04 |
Wafer to wafer bonding with low wafer distortion
Grant 10,720,345 - Kobrinsky , et al. | 2020-07-21 |
Compliant layer for wafer to wafer bonding
Grant 10,707,186 - Kobrinsky , et al. | 2020-07-07 |
Gate-all-around Integrated Circuit Structures Having Asymmetric Source And Drain Contact Structures
App 20200091348 - GUHA; Biswajeet ; et al. | 2020-03-19 |
Integrated Circuit Structures Having Differentiated Neighboring Partitioned Source Or Drain Contact Structures
App 20200075770 - KOBRINSKY; Mauro J. ; et al. | 2020-03-05 |
Integrated Circuit Structures Having Partitioned Source Or Drain Contact Structures
App 20200075771 - KOBRINSKY; Mauro J. ; et al. | 2020-03-05 |
Structure and method to self align via to top and bottom of tight pitch metal interconnect layers
Grant 10,553,532 - Schenker , et al. Fe | 2020-02-04 |
Pore-filled dielectric materials for semiconductor structure fabrication and their methods of fabrication
Grant 10,529,660 - Torres , et al. J | 2020-01-07 |
Deep Trench Via For Three-dimensional Integrated Circuit
App 20190378836 - WANG; Yih ; et al. | 2019-12-12 |
Microelectronic conductive routes and methods of making the same
Grant 10,497,613 - Chawla , et al. De | 2019-12-03 |
Stretchable electronics fabrication method with strain redistribution layer
Grant 10,468,357 - Dias , et al. No | 2019-11-05 |
Methods Of Forming Backside Self-aligned Vias And Structures Formed Thereby
App 20190326405 - Morrow; Patrick ; et al. | 2019-10-24 |
Integrated Circuit Device With Crenellated Metal Trace Layout
App 20190312023 - Morrow; Patrick ; et al. | 2019-10-10 |
Integrated Circuit Device With Back-side Inerconnection To Deep Source/drain Semiconductor
App 20190259699 - Morrow; Patrick ; et al. | 2019-08-22 |
Pore-filled Dielectric Materials For Semiconductor Structure Fabrication And Their Methods Of Fabrication
App 20190252313 - TORRES; Jessica M. ; et al. | 2019-08-15 |
Methods of forming backside self-aligned vias and structures formed thereby
Grant 10,367,070 - Morrow , et al. July 30, 2 | 2019-07-30 |
Backside Source/drain Replacement For Semiconductor Devices With Metallization On Both Sides
App 20190221649 - Glass; Glenn A. ; et al. | 2019-07-18 |
Backside Contact Resistance Reduction For Semiconductor Devices With Metallization On Both Sides
App 20190157310 - GLASS; GLENN A. ; et al. | 2019-05-23 |
Conductive Connectors Having A Ruthenium/aluminum-containing Liner And Methods Of Fabricating The Same
App 20190074217 - Jezewski; Christopher J. ; et al. | 2019-03-07 |
Transistor Cells Including A Deep Via Lined With A Dielectric Material
App 20190067091 - Morrow; Patrick ; et al. | 2019-02-28 |
Methods Of Forming Backside Self-aligned Vias And Structures Formed Thereby
App 20180248012 - Morrow; Patrick ; et al. | 2018-08-30 |
Optical I/O system using planar light-wave integrated circuit
Grant 10,054,737 - Kobrinsky , et al. August 21, 2 | 2018-08-21 |
Microelectronic Conductive Routes And Methods Of Making The Same
App 20180082942 - Chawla; Jasmeet S. ; et al. | 2018-03-22 |
Stretchable Electronics Fabrication Method With Strain Redistribution Layer
App 20180019213 - DIAS; Rajendra C. ; et al. | 2018-01-18 |
Structure And Method To Self Align Via To Top And Bottom Of Tight Pitch Metal Interconnect Layers
App 20170263553 - SCHENKER; RICHARD E. ; et al. | 2017-09-14 |
Techniques for enhancing fracture resistance of interconnects
Grant 9,691,716 - Jezewski , et al. June 27, 2 | 2017-06-27 |
Optical I/o System Using Planar Light-wave Integrated Circuit
App 20170131469 - Kobrinsky; Mauro J. ; et al. | 2017-05-11 |
Optical I/O system using planar light-wave integrated circuit
Grant 9,507,086 - Kobrinsky , et al. November 29, 2 | 2016-11-29 |
Techniques For Enhancing Fracture Resistance Of Interconnects
App 20160268218 - JEZEWSKI; CHRISTOPHER J. ; et al. | 2016-09-15 |
Metal-insulator-metal capacitor formation techniques
Grant 9,443,922 - Kobrinsky , et al. September 13, 2 | 2016-09-13 |
Techniques for enhancing fracture resistance of interconnects
Grant 9,343,411 - Jezewski , et al. May 17, 2 | 2016-05-17 |
Fabrication of planar light-wave circuits (PLCS) for optical I/O
Grant 9,182,544 - Kobrinsky , et al. November 10, 2 | 2015-11-10 |
Dielectric Layers Having Ordered Elongate Pores
App 20150170926 - Michalak; David J. ; et al. | 2015-06-18 |
Metal-insulator-metal Capacitor Formation Techniques
App 20150155349 - Kobrinsky; Mauro J. ; et al. | 2015-06-04 |
Optical waveguide structure
Grant 9,036,954 - Kobrinsky , et al. May 19, 2 | 2015-05-19 |
Metal-insulator-metal capacitor formation techniques
Grant 8,993,404 - Kobrinsky , et al. March 31, 2 | 2015-03-31 |
Techniques For Enhancing Fracture Resistance Of Interconnects
App 20140210098 - Jezewski; Christopher J. ; et al. | 2014-07-31 |
Metal-insulator-metal Capacitor Formation Techniques
App 20140203400 - Kobrinsky; Mauro J. ; et al. | 2014-07-24 |
Optical I/o System Using Planar Light-wave Integrated Circuit
App 20140203175 - Kobrinsky; Mauro J. ; et al. | 2014-07-24 |
Waveguide integration on laser for alignment-tolerant assembly
Grant 8,731,346 - Tseng , et al. May 20, 2 | 2014-05-20 |
Poling Structures And Methods For Photonic Devices Employing Electro-optical Polymers
App 20140086523 - BLOCK; Bruce A. ; et al. | 2014-03-27 |
Waveguide Integration On Laser For Alignment-tolerant Assembly
App 20140003765 - Tseng; Jia-Hung ; et al. | 2014-01-02 |
Optical Coupling Techniques And Configurations Between Dies
App 20130336346 - Kobrinsky; Mauro J. ; et al. | 2013-12-19 |
Fabrication Of Planar Light-wave Circuits (plcs) For Optical I/o
App 20130279845 - Kobrinsky; Mauro J. ; et al. | 2013-10-24 |
Three-dimensional stacked substrate arrangements
Grant 8,421,225 - Ramanathan , et al. April 16, 2 | 2013-04-16 |
Three-dimensional Stacked Substrate Arrangements
App 20120280387 - Ramanathan; Shriram ; et al. | 2012-11-08 |
Optical Waveguide Structure
App 20120251029 - KOBRINSKY; MAURO J. ; et al. | 2012-10-04 |
Three-dimensional stacked substrate arrangements
Grant 8,203,208 - Ramanathan , et al. June 19, 2 | 2012-06-19 |
Three-dimensional Stacked Substrate Arrangements
App 20110260319 - Ramanathan; Shriram ; et al. | 2011-10-27 |
Three-dimensional stacked substrate arrangements
Grant 7,973,407 - Ramanathan , et al. July 5, 2 | 2011-07-05 |
Method of forming self-passivating interconnects and resulting devices
Grant 7,402,509 - Kobrinsky , et al. July 22, 2 | 2008-07-22 |
Method and structure for interfacing electronic devices
Grant 7,348,217 - Kobrinsky , et al. March 25, 2 | 2008-03-25 |
Highly Compliant Plate For Wafer Bonding
App 20070287263 - Kobrinsky; Mauro J. ; et al. | 2007-12-13 |
Wafer bonding with highly compliant plate having filler material enclosed hollow core
Grant 7,307,005 - Kobrinsky , et al. December 11, 2 | 2007-12-11 |
Method and structure for interfacing electronic devices
App 20070015340 - Kobrinsky; Mauro J. ; et al. | 2007-01-18 |
Method and apparatus for bonding wafers
App 20060292823 - Ramanathan; Shriram ; et al. | 2006-12-28 |
Method of signal distribution based on a standing wave within a closed loop path
Grant 7,120,817 - Kobrinsky , et al. October 10, 2 | 2006-10-10 |
Method of forming self-passivating interconnects and resulting devices
App 20060220197 - Kobrinsky; Mauro J. ; et al. | 2006-10-05 |
Differential planarization
Grant 7,105,925 - Boardman , et al. September 12, 2 | 2006-09-12 |
Highly compliant plate for wafer bonding
App 20060003547 - Kobrinsky; Mauro J. ; et al. | 2006-01-05 |
Highly compliant plate for wafer bonding
App 20060003548 - Kobrinsky; Mauro J. ; et al. | 2006-01-05 |
Method and structure for interfacing electronic devices
App 20050184400 - Kobrinsky, Mauro J. ; et al. | 2005-08-25 |
Differential planarization
App 20050170759 - Boardman, James A. ; et al. | 2005-08-04 |
Differential planarization
Grant 6,914,002 - Boardman , et al. July 5, 2 | 2005-07-05 |
Method and structure for interfacing electronic devices
Grant 6,870,270 - Kobrinsky , et al. March 22, 2 | 2005-03-22 |
Three-dimensional stacked substrate arrangements
App 20050003650 - Ramanathan, Shriram ; et al. | 2005-01-06 |
Methods for bonding wafers using a metal interlayer
App 20040262772 - Ramanathan, Shriram ; et al. | 2004-12-30 |
Closed loop based timing signal distribution architecture
App 20040243873 - Kobrinsky, Mauro J. ; et al. | 2004-12-02 |
Method and structure for interfacing electronic devices
App 20040232537 - Kobrinsky, Mauro J. ; et al. | 2004-11-25 |
Thinning techniques for wafer-to-wafer vertical stacks
Grant 6,790,748 - Kim , et al. September 14, 2 | 2004-09-14 |
Differential planarization
App 20040127049 - Boardman, James A. ; et al. | 2004-07-01 |
Thinning techniques for wafer-to-wafer vertical stacks
App 20040121556 - Kim, Sarah E. ; et al. | 2004-06-24 |
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