| Patent | Date |
|---|
Method of forming shallow trench isolation
App 20020182824 - Lin, Ying-Jen ; et al. | 2002-12-05 |
Semiconductor device with an anti-doped region
App 20020089021 - Ko, Joe | 2002-07-11 |
Method for forming a self-aligned silicide layer
Grant 6,350,677 - Ko , et al. February 26, 2 | 2002-02-26 |
Method for manufacturing capacitor
Grant 6,303,455 - Hou , et al. October 16, 2 | 2001-10-16 |
Method of fabricating a mixed circuit capacitor
Grant 6,271,082 - Hou , et al. August 7, 2 | 2001-08-07 |
Method of stabilizing anti-reflection coating layer
Grant 6,225,219 - Lee , et al. May 1, 2 | 2001-05-01 |
Method for fabricating flash memory
Grant 6,194,271 - Lin , et al. February 27, 2 | 2001-02-27 |
Method of fabricating electrostatic discharge protection device
Grant 5,960,288 - Hong , et al. September 28, 1 | 1999-09-28 |
Process of forming a field effect transistor without spacer mask edge defects
Grant 5,956,590 - Hsieh , et al. September 21, 1 | 1999-09-21 |
Buried structure SRAM cell and methods for fabrication
Grant 5,821,629 - Wen , et al. October 13, 1 | 1998-10-13 |
Local punchthrough stop for ultra large scale integration devices
Grant 5,686,321 - Ko , et al. November 11, 1 | 1997-11-11 |
Retarded double diffused drain device structure
Grant 5,654,569 - Ko August 5, 1 | 1997-08-05 |
Method for ESD protection circuit with deep source diffusion
Grant 5,646,062 - Yuan , et al. July 8, 1 | 1997-07-08 |
Complementary LVTSCR ESD protection circuit for sub-micron CMOS integrated circuits
Grant 5,576,557 - Ker , et al. November 19, 1 | 1996-11-19 |
Field effect transistor structure of a diving channel device
Grant 5,574,302 - Wen , et al. November 12, 1 | 1996-11-12 |
Surface counter doped N-LDD for high carrier reliability
Grant 5,565,700 - Chou , et al. October 15, 1 | 1996-10-15 |
Maskless method for formation of a field implant channel stop region
Grant 5,518,941 - Lin , et al. May 21, 1 | 1996-05-21 |
Self-aligned anti-punchthrough implantation process
Grant 5,484,743 - Ko , et al. January 16, 1 | 1996-01-16 |
Complementary-SCR electrostatic discharge protection circuit
Grant 5,473,169 - Ker , et al. December 5, 1 | 1995-12-05 |
Grounding method to eliminate the antenna effect in VLSI process
Grant 5,434,108 - Ko , et al. July 18, 1 | 1995-07-18 |
"Bird-beak-less" field isolation method
Grant 5,393,693 - Ko , et al. February 28, 1 | 1995-02-28 |
Layout design to eliminate process antenna effect
Grant 5,393,701 - Ko , et al. February 28, 1 | 1995-02-28 |
Method for ESD protection improvement
Grant 5,374,565 - Hsue , et al. December 20, 1 | 1994-12-20 |
Device for preventing antenna effect on circuit
Grant 5,350,710 - Hong , et al. September 27, 1 | 1994-09-27 |
Surface counter-doped N-LDD for high hot carrier reliability
Grant 5,308,780 - Chou , et al. May 3, 1 | 1994-05-03 |
CMOS ESD protection circuit with parasitic SCR structures
Grant 5,140,401 - Ker , et al. August 18, 1 | 1992-08-18 |
| 