loadpatents
name:-0.01868200302124
name:-0.0174400806427
name:-0.0017991065979004
Knoll; Ernest Patent Filings

Knoll; Ernest

Patent Applications and Registrations

Patent applications and USPTO patent grants for Knoll; Ernest.The latest application filed is for "clock frequency ratio monitor".

Company Profile
1.14.15
  • Knoll; Ernest - Haifa IL
  • Knoll; Ernest - Tirat Hacarmel IL
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Clock Frequency Ratio Monitor
App 20220091168 - Ben Simon; Yossi ;   et al.
2022-03-24
Device, System And Method To Detect Clock Skew
App 20220083093 - Ben Simon; Yossi ;   et al.
2022-03-17
Techniques in phase-lock loop configuration in a computing device
Grant 10,958,278 - Gur , et al. March 23, 2
2021-03-23
Techniques In Phase-lock Loop Configuration In A Computing Device
App 20210036708 - Gur; Ariel ;   et al.
2021-02-04
Changing The Clock Frequency Of A Computing Device
App 20170149554 - Gendler; Alexander ;   et al.
2017-05-25
Changing the clock frequency of a computing device
Grant 9,660,799 - Gendler , et al. May 23, 2
2017-05-23
Delay stage with controllably variable capacitive load
Grant 7,605,668 - Fayneh , et al. October 20, 2
2009-10-20
Temperature Compensated Loop Filter
App 20080157880 - Fayneh; Eyal ;   et al.
2008-07-03
Charge Pump Circuit
App 20080150596 - Fayneh; Eyal ;   et al.
2008-06-26
Delay Stage With Controllably Variable Capacitive Load
App 20080136545 - Fayneh; Eyal ;   et al.
2008-06-12
Method and apparatus for controlling power management state transitions
Grant 7,363,523 - Kurts , et al. April 22, 2
2008-04-22
Startup/yank circuit for self-biased phase-locked loops
Grant 7,265,637 - Knoll , et al. September 4, 2
2007-09-04
Startup/yank circuit for self-biased phase-locked loops
App 20060244542 - Knoll; Ernest ;   et al.
2006-11-02
High-accuracy continuous duty-cycle correction circuit
Grant 7,120,839 - Fayneh , et al. October 10, 2
2006-10-10
Yank detection circuit for self-biased phase locked loops
Grant 7,095,289 - Knoll , et al. August 22, 2
2006-08-22
Method and apparatus for controlling power management state transitions
App 20060047986 - Kurts; Tsvika ;   et al.
2006-03-02
Startup/yank circuit for self-biased phase-locked loops
App 20050206459 - Knoll, Ernest ;   et al.
2005-09-22
Startup/yank circuit for self-biased phase-locked loops
Grant 6,922,047 - Knoll , et al. July 26, 2
2005-07-26
Method for clock generator lock-time reduction during speedstep transition
Grant 6,914,490 - Fayneh , et al. July 5, 2
2005-07-05
High-performance charge pump for self-biased phase-locked loop
Grant 6,894,569 - Fayneh , et al. May 17, 2
2005-05-17
High-accuracy continuous duty-cycle correction circuit
App 20050044455 - Fayneh, Eyal ;   et al.
2005-02-24
Method for clock generator lock-time reduction during speedstep transition
App 20040251970 - Fayneh, Eyal ;   et al.
2004-12-16
Startup/yank circuit for self-biased phase-locked loops
App 20040239354 - Knoll, Ernest ;   et al.
2004-12-02
High-performance charge pump for self-biased phase-locked loop
App 20040124935 - Fayneh, Eyal ;   et al.
2004-07-01
On-chip filter-regulator, such as one for a microprocessor phase locked loop (PLL) supply
Grant 6,661,213 - Fayneh , et al. December 9, 2
2003-12-09
On-chip filter-regulator, such as one for a microprocessor phase locked loop (PLL) supply
App 20020030471 - Fayneh, Eyal ;   et al.
2002-03-14
Third-order self-biased phase-locked loop for low jitter applications
Grant 6,329,882 - Fayneh , et al. December 11, 2
2001-12-11
On-chip filter-regulator for a microprocessor phase locked loop supply
Grant 6,313,615 - Fayneh , et al. November 6, 2
2001-11-06
One-shot clock generator circuit
Grant 5,357,204 - Knoll October 18, 1
1994-10-18

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