| Patent | Date |
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Protection of electronic designs
Grant 11,232,219 - Ochotta , et al. January 25, 2 | 2022-01-25 |
Hardware acceleration device handoff for using programmable integrated circuits as hardware accelerators
Grant 9,864,828 - Puthana , et al. January 9, 2 | 2018-01-09 |
Software development-based compilation flow for hardware implementation
Grant 9,824,173 - An , et al. November 21, 2 | 2017-11-21 |
Constraint handling for parameterizable hardware description language
Grant 9,679,092 - Jha , et al. June 13, 2 | 2017-06-13 |
Linking of simulators into a circuit design tool
Grant 9,646,118 - Klair , et al. May 9, 2 | 2017-05-09 |
Programmable IC design creation using circuit board data
Grant 9,465,903 - Timmireddy , et al. October 11, 2 | 2016-10-11 |
Circuit module generation for programmable integrated circuits
Grant 8,938,704 - Rele , et al. January 20, 2 | 2015-01-20 |
Method and apparatus for unified out-of-context flow and automation for IP reuse and hierarchical design flows
Grant 8,839,166 - Chakraborty , et al. September 16, 2 | 2014-09-16 |
System and method for import and export of design constraints
Grant 8,612,916 - O'Higgins , et al. December 17, 2 | 2013-12-17 |
System and method for automated configuration of design constraints
Grant 8,549,454 - Kong , et al. October 1, 2 | 2013-10-01 |
Partitioning a large design across multiple devices
Grant 7,873,927 - Knol , et al. January 18, 2 | 2011-01-18 |
Strategies for generating an implementation of an electronic design
Grant 7,519,938 - Shortt , et al. April 14, 2 | 2009-04-14 |
Method of memory and run-time efficient hierarchical timing analysis in programmable logic devices
Grant 7,437,695 - Ranjan , et al. October 14, 2 | 2008-10-14 |
System for representing the logical and physical information of an integrated circuit
Grant 7,418,686 - Knol , et al. August 26, 2 | 2008-08-26 |
Partitioning a large design across multiple devices
Grant 7,370,302 - Knol , et al. May 6, 2 | 2008-05-06 |
Data structures for representing the logical and physical information of an integrated circuit
Grant 7,146,595 - Knol , et al. December 5, 2 | 2006-12-05 |
Process for adjusting data structures of a floorplan upon changes occurring
Grant 7,120,892 - Knol , et al. October 10, 2 | 2006-10-10 |
System for creating a physical hierarchy of a chip without restriction by invading a logical hierarchy of logic blocks
Grant 7,117,473 - Knol , et al. October 3, 2 | 2006-10-03 |
System for representing the logical and physical information of an integrated circuit
Grant 7,073,149 - Knol , et al. July 4, 2 | 2006-07-04 |
Data structures for representing the logical and physical information of an integrated circuit
App 20050204315 - Knol, David A. ; et al. | 2005-09-15 |
System for representing the logical and physical information of an integrated circuit
App 20050198605 - Knol, David A. ; et al. | 2005-09-08 |
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