Knechtel; Roy

Patent Applications and Registrations

Patent applications and USPTO patent grants for Knechtel; Roy.The latest application filed is for "anodic bonding of a substrate of glass having contact vias to a substrate of silicon".

Company Profile

6.7.14

Knechtel; Roy - Geraberg DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Anodic bonding of a substrate of glass having contact vias to a substrate of silicon Grant 11,398,452 - Weinberger , et al. July 26, 2	2022-07-26
Electrically conductive via(s) in a semiconductor substrate and associated production method Grant 10,825,728 - Knechtel , et al. November 3, 2	2020-11-03
Anodic Bonding of a Substrate of Glass having Contact Vias to a Substrate of Silicon App 20200258863 - A1	2020-08-13
Anodic Bonding of a Substrate of Glass having Contact Vias to a Substrate of Silicon App 20200258862 - A1	2020-08-13
Anodic Bonding of a Substrate of Glass having Contact Vias to a Substrate of Silicon App 20200118967 - WEINBERGER; Stefan ; et al.	2020-04-16
Electrically Conductive Via(s) In A Semiconductor Substrate And Associated Production Method App 20190198395 - Knechtel; Roy ; et al.	2019-06-27
Electrically conductive via(s) in a semiconductor substrate and associated production method Grant 10,199,274 - Knechtel , et al. Fe	2019-02-05
Electrical Conductive Vias In A Semiconductor Substrate And A Corresponding Manufacturing Method App 20170294351 - Knechtel; Roy ; et al.	2017-10-12
Firm, insulating and electrically conducting connection of processed semiconductor wafers Grant 8,129,255 - Knechtel March 6, 2	2012-03-06
Hermetic sealing and electrical contacting of a microelectromechanical structure, and microsystem (MEMS) produced therewith Grant 8,021,906 - Knechtel September 20, 2	2011-09-20
Method For Transferring An Epitaxial Layer From A Donor Wafer To A System Wafer Appertaining To Microsystems Technology App 20100330506 - Knechtel; Roy	2010-12-30
Structured Layer Deposition On Processed Wafers Used In Microsystem Technology App 20100311248 - Knechtel; Roy	2010-12-09
Production Of Adjustment Structures For A Structured Layer Deposition On A Microsystem Technology Wafer App 20100282165 - Knechtel; Roy	2010-11-11
Production of semiconductor substrates with buried layers by joining (bonding) semiconductor wafers Grant 7,790,569 - Knechtel , et al. September 7, 2	2010-09-07
Hermetic Sealing And Electrical Contacting Of A Microelectromechanical Structure, And Microsystem (mems) Produced Therewith App 20100096712 - Knechtel; Roy	2010-04-22
Electrical determination of the connection quality of a bonded wafer connection Grant 7,509,875 - Knechtel March 31, 2	2009-03-31
Production Of Semiconductor Substrates With Buried Layers By Joining (Bonding) Semiconductor Wafers App 20080036041 - Knechtel; Roy ; et al.	2008-02-14
Method and Device For Secure, Insulated and Electrically Conductive Assembling Of Treated Semiconductor Wafers App 20080029878 - Knechtel; Roy	2008-02-07
Electrical Determination Of The Connection Quality Of A Bonded Wafer Connection App 20080011096 - Knechtel; Roy	2008-01-17
Separating semiconductor wafers having exposed micromechanical structures into individual chips App 20070031989 - Knechtel; Roy ; et al.	2007-02-08
Production of an optoelectronic component that is enclosed in plastic, and corresponding methods App 20060124915 - Buettner; Siegfried ; et al.	2006-06-15

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