Knapp; Steven K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Knapp; Steven K..The latest application filed is for "reconfigurable processor circuit architecture".

Company Profile

1.15.1

Knapp; Steven K. - Soquel CA
Knapp; Steven K. - Aptos CA
Knapp; Steven K. - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Reconfigurable Processor Circuit Architecture App 20210073171 - Master; Paul L. ; et al.	2021-03-11
Methods of authenticating a programmable integrated circuit in combination with a non-volatile memory device Grant 8,863,230 - Knapp , et al. October 14, 2	2014-10-14
Methods of authenticating a user design in a programmable integrated circuit Grant 7,987,358 - Walstrum, Jr. , et al. July 26, 2	2011-07-26
Authentication for information provided to an integrated circuit Grant 7,768,293 - Knapp August 3, 2	2010-08-03
Authentication for information provided to an integrated circuit Grant 7,535,249 - Knapp May 19, 2	2009-05-19
Method to program non-JTAG attached devices or memories using a PLD and its associated JTAG interface Grant 7,454,556 - Knapp November 18, 2	2008-11-18
Parallel interface for configuring programmable devices Grant 7,358,762 - Walstrum, Jr. , et al. April 15, 2	2008-04-15
Flexible scheme for configuring programmable semiconductor devices using or loading programs from SPI-based serial flash memories that support multiple SPI flash vendors and device families Grant 7,281,082 - Knapp October 9, 2	2007-10-09
Method and apparatus to copy protect software programs Grant 7,243,227 - Knapp July 10, 2	2007-07-10
Bus mastering debugging system for integrated circuits Grant 6,691,266 - Winegarden , et al. February 10, 2	2004-02-10
Method of optimizing resource allocation starting from a high level block diagram Grant 5,737,234 - Seidel , et al. April 7, 1	1998-04-07
Method of allocating logic using general function components Grant 5,574,655 - Knapp , et al. November 12, 1	1996-11-12
Method for optimizing resource allocation starting from a high level Grant 5,553,001 - Seidel , et al. September 3, 1	1996-09-03
Method for generating logic modules from a high level block diagram Grant 5,499,192 - Knapp , et al. March 12, 1	1996-03-12
Method and system for propagating data type for circuit design from a high level block diagram Grant 5,422,833 - Kelem , et al. June 6, 1	1995-06-06

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.