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name:-0.044445991516113
name:-0.034296035766602
name:-0.00065898895263672
Knall; N. Johan Patent Filings

Knall; N. Johan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Knall; N. Johan.The latest application filed is for "reverse-bias method for writing memory cells in a memory array".

Company Profile
0.30.28
  • Knall; N. Johan - Sunnyvale CA US
  • Knall, N. Johan - Sunnyvals CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Silicon nitride antifuse for use in diode-antifuse memory arrays
Grant 8,575,719 - Johnson , et al. November 5, 2
2013-11-05
Process for fabricating a dielectric film using plasma oxidation
Grant 7,816,188 - Vyvoda , et al. October 19, 2
2010-10-19
Electrically isolated pillars in active devices
Grant 7,413,945 - Vyvoda , et al. August 19, 2
2008-08-19
Reverse-bias method for writing memory cells in a memory array
Grant 7,304,888 - Knall December 4, 2
2007-12-04
Electrically isolated pillars in active devices
Grant 7,245,000 - Vyvoda , et al. July 17, 2
2007-07-17
Reverse-bias method for writing memory cells in a memory array
App 20070002610 - Knall; N. Johan
2007-01-04
Three-dimensional memory array and method of fabrication
Grant 7,091,529 - Knall , et al. August 15, 2
2006-08-15
Patterning three dimensional structures
Grant 7,071,565 - Li , et al. July 4, 2
2006-07-04
Manufacturing method for integrated circuit having disturb-free programming of passive element memory cells
Grant 7,022,572 - Scheuerlein , et al. April 4, 2
2006-04-04
Apparatus and method for disturb-free programming of passive element memory cells
Grant 6,963,504 - Scheuerlein , et al. November 8, 2
2005-11-08
Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions
Grant 6,954,394 - Knall , et al. October 11, 2
2005-10-11
Electrically isolated pillars in active devices
Grant 6,952,043 - Vyvoda , et al. October 4, 2
2005-10-04
Manufacturing method for integrated circuit having disturb-free programming of passive element memory cells
App 20050101088 - Scheuerlein, Roy E. ;   et al.
2005-05-12
Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication
Grant 6,888,750 - Walker , et al. May 3, 2
2005-05-03
Apparatus and method for disturb-free programming of passive element memory cells
App 20050073898 - Scheuerlein, Roy E. ;   et al.
2005-04-07
Apparatus and method for disturb-free programming of passive element memory cells
Grant 6,822,903 - Scheuerlein , et al. November 23, 2
2004-11-23
Three-dimensional memory array and method of fabrication
App 20040188798 - Knall, N. Johan ;   et al.
2004-09-30
Apparatus and method for disturb-free programming of passive element memory cells
App 20040190359 - Scheuerlein, Roy E. ;   et al.
2004-09-30
Memory cell with antifuse layer formed at diode junction
Grant 6,777,773 - Knall August 17, 2
2004-08-17
Thermal processing for three dimensional circuits
Grant 6,770,939 - Subramanian , et al. August 3, 2
2004-08-03
Formation of antifuse structure in a three dimensional memory
Grant 6,768,185 - Cleeves , et al. July 27, 2
2004-07-27
Method for making a three-dimensional memory array incorporating serial chain diode stack
Grant 6,767,816 - Kleveland , et al. July 27, 2
2004-07-27
Integrated circuit and method for selecting a set of memory-cell-layer-dependent or temperature-dependent operating conditions
App 20040100831 - Knall, N. Johan ;   et al.
2004-05-27
Three-dimensional memory array and method of fabrication
App 20040089917 - Knall, N. Johan ;   et al.
2004-05-13
Electrically isolated pillars in active devices
App 20040087072 - Vyvoda, Michael A. ;   et al.
2004-05-06
Electrically isolated pillars in active devices
App 20040071034 - Vyvoda, Michael A. ;   et al.
2004-04-15
Anti-fuse memory cell with asymmetric breakdown voltage
Grant 6,704,235 - Knall , et al. March 9, 2
2004-03-09
Silicon nitride antifuse for use in diode-antifuse memory arrays
App 20040016991 - Johnson, Mark G. ;   et al.
2004-01-29
Electrically Isolated Pillars In Active Devices
App 20040002186 - Vyvoda, Michael A. ;   et al.
2004-01-01
Three-dimensional memory array and method of fabrication
Grant 6,653,712 - Knall , et al. November 25, 2
2003-11-25
Same conductivity type highly-doped regions for antifuse memory cell
Grant 6,642,603 - Knall November 4, 2
2003-11-04
Three-dimensional memory array incorporating serial chain diode stack
Grant 6,631,085 - Kleveland , et al. October 7, 2
2003-10-07
Patterning three dimensional structures
Grant 6,627,530 - Li , et al. September 30, 2
2003-09-30
Thermal processing for three dimensional circuits
Grant 6,624,011 - Subramanian , et al. September 23, 2
2003-09-23
Formation of antifuse structure in a three dimensional memory
Grant 6,541,312 - Cleeves , et al. April 1, 2
2003-04-01
Three-dimensional memory array incorporating serial chain diode stack
App 20030053332 - Kleveland, Bendik ;   et al.
2003-03-20
Anti-fuse memory cell with asymmetric breakdown voltage
App 20030026157 - Knall, N. Johan ;   et al.
2003-02-06
Patterning three dimensional structures
App 20030025210 - Li, Calvin K. ;   et al.
2003-02-06
Thermal processing for three dimensional circuits
App 20030025176 - Subramanian, Vivek ;   et al.
2003-02-06
Anti-fuse memory cell with asymmetric breakdown voltage
App 20030026158 - Knall, N. Johan ;   et al.
2003-02-06
Low cost three-dimensional memory array
Grant 6,515,888 - Johnson , et al. February 4, 2
2003-02-04
Process for fabricating a dielectric film using plasma oxidation
App 20030022526 - Vyvoda, Michael A. ;   et al.
2003-01-30
Three-dimensional memory array incorporating serial chain diode stack
App 20030022420 - Kleveland, Bendik ;   et al.
2003-01-30
Memory cell with antifuse layer formed at diode junction
App 20030021142 - Knall, N. Johan
2003-01-30
Formation of antifuse structure in a three dimensional memory
App 20030003632 - Cleeves, James M. ;   et al.
2003-01-02
Method of forming nonvolatile memory device utilizing a hard mask
Grant 6,486,065 - Vyvoda , et al. November 26, 2
2002-11-26
Three-dimensional memory array and method of fabrication
App 20020140051 - Knall, N. Johan ;   et al.
2002-10-03
Formation of antifuse structure in a three dimensional memory
App 20020106838 - Cleeves, James M. ;   et al.
2002-08-08
Three-dimensional memory array and method of fabrication
Grant 6,420,215 - Knall , et al. July 16, 2
2002-07-16
Three-dimensional Memory Array And Method Of Fabrication
App 20020088998 - Knall, N. Johan ;   et al.
2002-07-11
Method Of Forming Nonvolatile Memory Device Utilizing A Hard Mask
App 20020081851 - Vyvoda, Michael A. ;   et al.
2002-06-27
Patterning three dimensional structures
App 20020081833 - Li, Calvin K. ;   et al.
2002-06-27
Low-cost three-dimensional memory array
App 20020075719 - Johnson, Mark G. ;   et al.
2002-06-20
Arithmetic unit
App 20020038202 - Ferroussat, Sebastien ;   et al.
2002-03-28
Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication
App 20010055838 - Walker, Andrew J. ;   et al.
2001-12-27
Electron-emitting device having multi-layer resistor
Grant 6,013,986 - Knall , et al. January 11, 2
2000-01-11
Cleaning of electron-emissive elements
Grant 6,004,180 - Knall , et al. December 21, 1
1999-12-21

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