Kluth; George J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kluth; George J..The latest application filed is for "devices with slotted active regions".

Company Profile

3.21.8

Kluth; George J. - Saratoga Springs NY
Kluth; George J. - Hopewell Junction NY US
Kluth; George J. - Campbell CA
Kluth; George J. - Los Gatos CA
Kluth; George J. - Sunnyvale CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Fully depleted devices with slots in active regions Grant 11,239,087 - Yang , et al. February 1, 2	2022-02-01
Layouts for connecting contacts with metal tabs or vias Grant 10,691,862 - Nayyar , et al.	2020-06-23
Devices With Slotted Active Regions App 20200058515 - YANG; Heng ; et al.	2020-02-20
Devices with slotted active regions Grant 10,497,576 - Yang , et al. De	2019-12-03
Design Layouts For Connecting Contacts With Metal Tabs Or Vias App 20190012422 - NAYYAR; Neha ; et al.	2019-01-10
Semiconductor device with isolation trench liner Grant 8,716,828 - Carter , et al. May 6, 2	2014-05-06
Semiconductor Device With Isolation Trench Liner App 20120223399 - CARTER; Richard J. ; et al.	2012-09-06
Semiconductor device with isolation trench liner Grant 8,217,472 - Carter , et al. July 10, 2	2012-07-10
Semiconductor Device With Isolation Trench Liner App 20110260263 - CARTER; Richard J. ; et al.	2011-10-27
Semiconductor device with isolation trench liner, and related fabrication methods Grant 7,998,832 - Carter , et al. August 16, 2	2011-08-16
Integrated circuit having long and short channel metal gate devices and method of manufacture Grant 7,902,599 - Carter , et al. March 8, 2	2011-03-08
Integrated circuit long and short channel metal gate devices and method of manufacture Grant 7,723,192 - Carter , et al. May 25, 2	2010-05-25
Semiconductor Device With Isolation Trench Liner, And Related Fabrication Methods App 20100052094 - Carter; Richard J. ; et al.	2010-03-04
Integrated Circuit Having Long And Short Channel Metal Gate Devices And Method Of Manufacture App 20100044782 - CARTER; Richard J. ; et al.	2010-02-25
Integrated Circuit Long And Short Channel Metal Gate Devices And Method Of Manufacture App 20090230463 - CARTER; Richard J. ; et al.	2009-09-17
CMOS gates formed by integrating metals having different work functions and having a high-k gate dielectric Grant 7,176,531 - Xiang , et al. February 13, 2	2007-02-13
Memory cell structure having nitride layer with reduced charge loss and method for fabricating same Grant 6,992,370 - Kluth , et al. January 31, 2	2006-01-31
Method for forming polysilicon gate on high-k dielectric and related structure Grant 6,902,977 - Kluth , et al. June 7, 2	2005-06-07
Method for integrating metals having different work functions to form CMOS gates having a high-k gate dielectric and related structure Grant 6,872,613 - Xiang , et al. March 29, 2	2005-03-29
Method For Integrating Metals Having Different Work Functions To Fom Cmos Gates Having A High-k Gate Dielectric And Related Structure App 20050054149 - Xiang, Qi ; et al.	2005-03-10
Two-step process for nickel deposition Grant 6,841,449 - Bertrand , et al. January 11, 2	2005-01-11
Two-step process for nickel deposition Grant 6,689,687 - Bertrand , et al. February 10, 2	2004-02-10
Two-step process for nickel deposition Grant 6,632,740 - Bertrand , et al. October 14, 2	2003-10-14
Stacked double sidewall spacer oxide over nitride Grant 6,627,504 - Bertrand , et al. September 30, 2	2003-09-30
Nitrogen implant into nitride spacer to reduce nickel silicide formation on spacer Grant 6,602,754 - Kluth , et al. August 5, 2	2003-08-05
Process for forming fully silicided gates Grant 6,562,718 - Xiang , et al. May 13, 2	2003-05-13
Fully nickel silicided metal gate with shallow junction formed Grant 6,555,453 - Xiang , et al. April 29, 2	2003-04-29
Cobalt barrier for nickel silicidation of a gate electrode Grant 6,541,866 - Bertrand , et al. April 1, 2	2003-04-01

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