loadpatents
name:-0.021038055419922
name:-0.039433002471924
name:-0.00069999694824219
Klim; Peter Juergen Patent Filings

Klim; Peter Juergen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Klim; Peter Juergen.The latest application filed is for "hybrid keeper circuit for dynamic logic".

Company Profile
0.35.17
  • Klim; Peter Juergen - Austin TX
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Transient noise detection scheme and apparatus
Grant 7,506,230 - Chu , et al. March 17, 2
2009-03-17
Hybrid Keeper Circuit for Dynamic Logic
App 20080116938 - Ngo; Hung C. ;   et al.
2008-05-22
Processor including a register file and method for computing flush masks in a multi-threaded processing system
Grant 7,266,675 - Burky , et al. September 4, 2
2007-09-04
Leakage sensing and keeper circuit for proper operation of a dynamic circuit
Grant 7,202,704 - Chu , et al. April 10, 2
2007-04-10
Methods and systems for performing horological functions using time cells
Grant 7,173,882 - Berstis , et al. February 6, 2
2007-02-06
Register file method incorporating read-after-write blocking using detection cells
Grant 7,142,463 - Chu , et al. November 28, 2
2006-11-28
Transient noise detection scheme and apparatus
App 20060184852 - Chu; Sam Gat-Shang ;   et al.
2006-08-17
Apparatus and method for dependency tracking and register file bypass controls using a scannable register file
App 20060168393 - Christensen; Bjorn Peter ;   et al.
2006-07-27
Processor including a register file and method for computing flush masks in a multi-threaded processing system
App 20060155966 - Burky; William Elton ;   et al.
2006-07-13
Register file apparatus and method for computing flush masks in a multi-threaded processing system
Grant 7,015,718 - Burky , et al. March 21, 2
2006-03-21
Dynamic-static logical control element for signaling an interval between the end of a control signal and a logical evaluation
Grant 7,015,723 - Chu , et al. March 21, 2
2006-03-21
Register file apparatus and method incorporating read-after-write blocking using detection cells
Grant 7,012,839 - Chu , et al. March 14, 2
2006-03-14
Leakage sensing and keeper circuit for proper operation of a dynamic circuit
App 20060049850 - Chu; Sam Gat-Shang ;   et al.
2006-03-09
Dynamic-static Logical Control Element For Signaling An Interval Between The End Of A Control Signal And A Logical Evaluation
App 20060038588 - Chu; Sam Gat-Shang ;   et al.
2006-02-23
Register file method incorporating read-after-write blocking using detection cells
App 20060039202 - Chu; Sam Gat-Shang ;   et al.
2006-02-23
Register File Apparatus And Method Incorporating Read-after-write Blocking Using Detection Cells
App 20060039203 - Chu; Sam Gat-Shang ;   et al.
2006-02-23
Multilevel register-file bit-read method and apparatus
Grant 7,002,860 - Chu , et al. February 21, 2
2006-02-21
Methods and systems for performing horological functions using time cells
App 20050185515 - Berstis, Viktors ;   et al.
2005-08-25
Reducing sub-threshold leakage in a memory array
Grant 6,934,181 - Chu , et al. August 23, 2
2005-08-23
Register-file bit-read method and apparatus
Grant 6,914,450 - Chu , et al. July 5, 2
2005-07-05
Register-file Bit-read Method And Apparatus
App 20050099205 - Chu, Sam Gat-Shang ;   et al.
2005-05-12
Multilevel register-file bit-read method and apparatus
App 20050099851 - Chu, Sam Gat-Shang ;   et al.
2005-05-12
Batteryless, oscillatorless, binary time cell usable as an horological device with associated programming methods and devices
Grant 6,856,581 - Berstis , et al. February 15, 2
2005-02-15
Batteryless, osciliatorless, analog time cell usable as an horological device with associated programming methods and devices
Grant 6,831,879 - Berstis , et al. December 14, 2
2004-12-14
Apparatus And Method For A Radiation Resistant Latch With Integrated Scan
App 20040250184 - Chu, Sam Gat-Shang ;   et al.
2004-12-09
Apparatus And Method For A Radiation Resistant Latch
App 20040246782 - Chu, Sam Gat-Shang ;   et al.
2004-12-09
Sensing methods and devices for a batteryless, oscillatorless, binary time cell usable as an horological device
Grant 6,829,200 - Berstis , et al. December 7, 2
2004-12-07
Apparatus and method for a radiation resistant latch with integrated scan
Grant 6,825,691 - Chu , et al. November 30, 2
2004-11-30
Apparatus and method for a radiation resistant latch
Grant 6,826,090 - Chu , et al. November 30, 2
2004-11-30
Sensing methods and devices for a batteryless, oscillatorless, analog time cell usable as an horological device
Grant 6,826,128 - Berstis , et al. November 30, 2
2004-11-30
Register file apparatus and method for computing flush masks in a multi-threaded processing system
App 20040208066 - Burky, William Elton ;   et al.
2004-10-21
Multistage, Single-rail Logic Circuitry And Method Therefore
App 20040178825 - Amatangelo, Matthew J. ;   et al.
2004-09-16
Multistage, single-rail logic circuitry and method therefore
Grant 6,791,363 - Amatangelo , et al. September 14, 2
2004-09-14
Self power audit and control circuitry for microprocessor functional units
Grant 6,785,826 - Durham , et al. August 31, 2
2004-08-31
Reducing sub-threshold leakage in a memory array
App 20040156227 - Chu, Sam Gat-Shang ;   et al.
2004-08-12
Register file with delayed parity check
Grant 6,701,484 - Jordan , et al. March 2, 2
2004-03-02
Register file timing using static timing tools
Grant 6,654,937 - Amatangelo , et al. November 25, 2
2003-11-25
Data processing system, method, and product for automatically performing timing checks on a memory cell using a static timing tool
Grant 6,650,592 - Amatangelo , et al. November 18, 2
2003-11-18
Data processing system, method, and product for automatically performing timing checks on a memory cell using a static timing tool
App 20030099129 - Amatangelo, Matthew J. ;   et al.
2003-05-29
Self-timed CMOS static logic circuit
Grant 6,522,170 - Durham , et al. February 18, 2
2003-02-18
Content addressable storage apparatus and register mapper architecture
Grant 6,480,931 - Buti , et al. November 12, 2
2002-11-12
Master-slave flip-flop circuit with embedded hold function and method for holding data in a master-slave flip-flop circuit
Grant 6,445,236 - Bernard , et al. September 3, 2
2002-09-03
Method and system for detecting errors within complementary logic circuits
Grant 6,253,350 - Durham , et al. June 26, 2
2001-06-26
Coupling noise reduction technique using reset timing
Grant 6,189,133 - Durham , et al. February 13, 2
2001-02-13
Power consumption control mechanism and method therefor
Grant 6,147,508 - Beck , et al. November 14, 2
2000-11-14
Self-timed address decoder for register file and compare circuit of a multi-port CAM
Grant 6,072,746 - Durham , et al. June 6, 2
2000-06-06
Logical steering to avoid hot spots on integrated circuits
Grant 6,000,036 - Durham , et al. December 7, 1
1999-12-07
Power down system and method for pipelined logic functions
Grant 5,983,339 - Klim November 9, 1
1999-11-09
Elastic self-timed interface for data flow elements embodied as selective bypass of stages in an asynchronous microprocessor pipeline
Grant 5,964,866 - Durham , et al. October 12, 1
1999-10-12
System and method for reducing power consumption in high frequency clocked circuits
Grant 5,761,517 - Durham , et al. June 2, 1
1998-06-02
Dynamic control of power consumption in self-timed circuits
Grant 5,737,614 - Durham , et al. April 7, 1
1998-04-07
High speed pipeline method and apparatus
Grant 5,732,233 - Klim , et al. March 24, 1
1998-03-24

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed