Kittl; Jorge

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kittl; Jorge.The latest application filed is for "optimization of sparsified neural network layers for semi-digital crossbar architectures".

Company Profile

8.15.14

Kittl; Jorge - Austin TX
Kittl; Jorge - Garland TX
Kittl; Jorge - Round Rock TX
Kittl; Jorge - Hamme-Mille N/A BE
Kittl; Jorge - Waterloo BE
KITTL, JORGE - PLANO TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
4T4R ternary weight cell with high on/off ratio background Grant 11,182,686 - Hatcher , et al. November 23, 2	2021-11-23
System and method for efficient enhancement of an on/off ratio of a bitcell based on 3T2R binary weight cell with spin orbit torque MJTs (SOT-MTJs) Grant 11,101,320 - Hatcher , et al. August 24, 2	2021-08-24
Optimization Of Sparsified Neural Network Layers For Semi-digital Crossbar Architectures App 20210133544 - Hatcher; Ryan ; et al.	2021-05-06
3t2r Binary Weight Cell With High On/off For Memory Device Programmed With Transverse Currents App 20210118950 - Hatcher; Ryan ; et al.	2021-04-22
Variation Mitigation Scheme For Semi-digital Mac Array With A 2t-2 Resistive Memory Element Bitcell App 20210057011 - HATCHER; Ryan ; et al.	2021-02-25
2T2R binary weight cell with high on/off ratio background Grant 10,872,662 - Hatcher , et al. December 22, 2	2020-12-22
Variation resistant 3T3R binary weight cell with low output current and high on/off ratio Grant 10,832,774 - Hatcher , et al. November 10, 2	2020-11-10
Variation Resistant 3t3r Binary Weight Cell With Low Output Current And High On/off Ratio App 20200279605 - Hatcher; Ryan M. ; et al.	2020-09-03
4t4r Ternary Weight Cell With High On/off Ratio Background App 20200279176 - HATCHER; Ryan M. ; et al.	2020-09-03
2t2r Binary Weight Cell With High On/off Ratio Background App 20200265892 - HATCHER; Ryan M. ; et al.	2020-08-20
Low-k dielectric pore sealant and metal-diffusion barrier formed by doping and method for forming the same Grant 10,510,665 - Hegde , et al. Dec	2019-12-17
S/D connection to individual channel layers in a nanosheet FET Grant 9,653,287 - Rodder , et al. May 16, 2	2017-05-16
0T bi-directional memory cell Grant 9,614,002 - Hatcher , et al. April 4, 2	2017-04-04
Low-k Dielectric Pore Sealant And Metal-diffusion Barrier Formed By Doping And Method For Forming The Same App 20160148870 - HEGDE; Ganesh ; et al.	2016-05-26
Metal-insulator-metal capacitor and method for manufacturing thereof Grant 9,343,298 - Popovici , et al. May 17, 2	2016-05-17
S/d Connection To Individual Channel Layers In A Nanosheet Fet App 20160126310 - RODDER; Mark ; et al.	2016-05-05
Method of manufacturing low resistivity contacts on n-type germanium Grant 9,177,812 - Martens , et al. November 3, 2	2015-11-03
Method for producing a metal-insulator-metal capacitor for use in semiconductor devices Grant 8,649,154 - Popovici , et al. February 11, 2	2014-02-11
Dielectric layer for flash memory device and method for manufacturing thereof Grant 8,405,166 - Adelmann , et al. March 26, 2	2013-03-26
Method of Manufacturing Low Resistivity Contacts on n-Type Germanium App 20120138928 - Martens; Koen ; et al.	2012-06-07
Metal-Insulator-Metal Capacitor and Method for Manufacturing Thereof App 20120092807 - Popovici; Mihaela Ioana ; et al.	2012-04-19
Method for Producing a Metal-Insulator-Metal Capacitor for Use in Semiconductor Devices App 20120075767 - Popovici; Mihaela Ioana ; et al.	2012-03-29
Dielectric Layer For Flash Memory Device And Method For Manufacturing Thereof App 20110147900 - Adelmann; Christoph ; et al.	2011-06-23
Method for Forming a Memory Cell Comprising a Capacitor Having a Strontium Titaniumoxide Based Dielectric Layer and Devices Obtained Thereof App 20100072531 - Kittl; Jorge ; et al.	2010-03-25
Method Of Forming A Silicide Layer Using Metallic Impurities And Pre-amorphization App 20020045307 - KITTL, JORGE ; et al.	2002-04-18

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