Kirsch; Howard C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kirsch; Howard C..The latest application filed is for "double gated 4f2 dram chc cell and methods of fabricating the same".

Company Profile

1.87.47

Kirsch; Howard C. - Eagle ID
Kirsch; Howard C. - Austin TX
Kirsch; Howard C. - Taoyuan TW
Kirsch; Howard C. - Emmaus PA
Kirsch; Howard C. - Colorado Springs CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Double gated 4F2 dram CHC cell and methods of fabricating the same Grant 9,472,461 - Juengling , et al. October 18, 2	2016-10-18
Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers Grant 9,190,126 - Thompson , et al. November 17, 2	2015-11-17
Memory device word line drivers and methods Grant 9,159,392 - Kim , et al. October 13, 2	2015-10-13
Apparatuses and methods for adjusting deactivation voltages Grant 9,082,466 - Xia , et al. July 14, 2	2015-07-14
Apparatuses and methods for reducing current leakage in a memory Grant 9,076,501 - Xia , et al. July 7, 2	2015-07-07
Double Gated 4f2 Dram Chc Cell And Methods Of Fabricating The Same App 20150093869 - Juengling; Werner ; et al.	2015-04-02
Double gated 4F2 dram CHC cell and methods of fabricating the same Grant 8,962,401 - Juengling , et al. February 24, 2	2015-02-24
Apparatuses And Methods For Reducing Current Leakage In A Memory App 20150049565 - Xia; Zhong-yi ; et al.	2015-02-19
Apparatuses And Methods For Adjusting Deactivation Voltages App 20150029804 - Xia; Zhong-Yi ; et al.	2015-01-29
Double gated 4F2 dram CHC cell and methods of fabricating the same Grant 8,921,899 - Juengling , et al. December 30, 2	2014-12-30
Memory Device Word Line Drivers And Methods App 20140226427 - Kim; Tae ; et al.	2014-08-14
Line driver circuits, methods, and apparatuses Grant 8,743,628 - Kim , et al. June 3, 2	2014-06-03
Memory device word line drivers and methods Grant 8,737,157 - Kim , et al. May 27, 2	2014-05-27
Transistor Voltage Threshold Mismatch Compensated Sense Amplifiers And Methods For Precharging Sense Amplifiers App 20140085992 - Thompson; J. Wayne ; et al.	2014-03-27
Transistor voltage threshold mismatch compensated sense amplifiers and methods for precharging sense amplifiers Grant 8,598,912 - Thompson , et al. December 3, 2	2013-12-03
Line Driver Circuits, Methods, And Apparatuses App 20130039132 - Kim; Tae H. ; et al.	2013-02-14
Double Gated 4f2 Dram Chc Cell And Methods Of Fabricating The Same App 20120205719 - Juengling; Werner ; et al.	2012-08-16
Double Gated 4f2 Dram Chc Cell And Methods Of Fabricating The Same App 20120126885 - Juengling; Werner ; et al.	2012-05-24
Memory structure having volatile and non-volatile memory portions Grant 8,149,619 - Kirsch , et al. April 3, 2	2012-04-03
Memory Device Word Line Drivers And Methods App 20120063256 - Kim; Tae ; et al.	2012-03-15
Devices and methods for a threshold voltage difference compensated sense amplifier Grant 8,111,570 - Kim , et al. February 7, 2	2012-02-07
Memory Device Word Line Drivers And Methods App 20110317509 - KIM; TAE ; et al.	2011-12-29
Transistor Voltage Threshold Mismatch Compensated Sense Amplifiers And Methods For Precharging Sense Amplifiers App 20110304358 - Thompson; J. Wayne ; et al.	2011-12-15
Memory Structure Having Volatile And Non-volatile Memory Portions App 20110127596 - Kirsch; Howard C. ; et al.	2011-06-02
Multiple-depth STI trenches in integrated circuit fabrication Grant 7,939,394 - Batra , et al. May 10, 2	2011-05-10
Memory structure having volatile and non-volatile memory portions Grant 7,898,857 - Kirsch , et al. March 1, 2	2011-03-01
Devices And Methods For A Threshold Voltage Difference Compensated Sense Amplifier App 20110032002 - Kim; Tae ; et al.	2011-02-10
Devices and methods for a threshold voltage difference compensated sense amplifier Grant 7,826,293 - Kim , et al. November 2, 2	2010-11-02
Memory Structure Having Volatile And Non-volatile Memory Portions App 20090237996 - Kirsch; Howard C. ; et al.	2009-09-24
Devices and methods for a threshold voltage difference compensated sense amplifier App 20090129188 - Kim; Tae ; et al.	2009-05-21
Open digit line array architecture for a memory array Grant 7,512,025 - Yoon , et al. March 31, 2	2009-03-31
Memory devices having reduced coupling noise between wordlines Grant 7,460,430 - Kim , et al. December 2, 2	2008-12-02
Level shifter for low voltage operation Grant 7,440,344 - Kim , et al. October 21, 2	2008-10-21
Methods of reducing coupling noise between wordlines Grant 7,417,916 - Kim , et al. August 26, 2	2008-08-26
Multiple-depth Sti Trenches In Integrated Circuit Fabrication App 20080176378 - Batra; Shubneesh ; et al.	2008-07-24
Open digit line array architecture for a memory array App 20080137458 - Yoon; Sei Seung ; et al.	2008-06-12
Trench buried bit line memory devices and methods thereof Grant 7,365,384 - Tran , et al. April 29, 2	2008-04-29
Multiple-depth STI trenches in integrated circuit fabrication Grant 7,354,812 - Batra , et al. April 8, 2	2008-04-08
Open digit line array architecture for a memory array Grant 7,345,937 - Yoon , et al. March 18, 2	2008-03-18
Open digit line array architecture for a memory array Grant 7,277,310 - Yoon , et al. October 2, 2	2007-10-02
Level shifter for low voltage operation App 20070195614 - Kim; Tae H. ; et al.	2007-08-23
Open digit line array architecture for a memory array Grant 7,254,074 - Yoon , et al. August 7, 2	2007-08-07
Level shifter for low voltage operation Grant 7,200,053 - Kim , et al. April 3, 2	2007-04-03
Open digit line array architecture for a memory array Grant 7,193,914 - Yoon , et al. March 20, 2	2007-03-20
Trench buried bit line memory devices and methods thereof App 20070040200 - Tran; Luan C. ; et al.	2007-02-22
Trench buried bit line memory devices and methods thereof Grant 7,170,124 - Tran , et al. January 30, 2	2007-01-30
Memory devices having reduced coupling noise between wordlines App 20060274596 - Kim; Tae H. ; et al.	2006-12-07
Open digit line array architecture for a memory array App 20060268638 - Yoon; Sei Seung ; et al.	2006-11-30
Open digit line array architecture for a memory array App 20060268640 - Yoon; Sei Seung ; et al.	2006-11-30
Open digit line array architecture for a memory array App 20060268639 - Yoon; Sei Seung ; et al.	2006-11-30
Memory devices having reduced coupling noise between wordlines App 20060262636 - Kim; Tae H. ; et al.	2006-11-23
Memory devices having reduced coupling noise between wordlines Grant 7,110,319 - Kim , et al. September 19, 2	2006-09-19
Open digit line array architecture for a memory array App 20060198220 - Yoon; Sei Seung ; et al.	2006-09-07
Voltage level shifting circuit and method App 20060176078 - Kim; Tae H. ; et al.	2006-08-10
Voltage level shifting circuit and method Grant 7,034,572 - Kim , et al. April 25, 2	2006-04-25
Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage Grant 7,023,751 - Kirsch April 4, 2	2006-04-04
Level shifter for low voltage operation App 20060044888 - Kim; Tae H. ; et al.	2006-03-02
Memory devices having reduced coupling noise between wordlines App 20060044921 - Kim; Tae H. ; et al.	2006-03-02
Multiple-depth STI trenches in integrated circuit fabrication App 20060043455 - Batra; Shubneesh ; et al.	2006-03-02
Voltage level shifting circuit and method App 20050275430 - Kim, Tae H. ; et al.	2005-12-15
Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays Grant 6,934,208 - Thompson , et al. August 23, 2	2005-08-23
Method and system for accelerating coupling of digital signals Grant 6,925,019 - Kirsch August 2, 2	2005-08-02
Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line Grant 6,924,686 - Kirsch August 2, 2	2005-08-02
Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage App 20050141309 - Kirsch, Howard C.	2005-06-30
Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage Grant 6,888,769 - Kirsch May 3, 2	2005-05-03
Trench buried bit line memory devices and methods thereof App 20050078534 - Tran, Luan C. ; et al.	2005-04-14
System and method to avoid voltage read errors in open digit line array dynamic random access memories Grant 6,856,530 - Kirsch February 15, 2	2005-02-15
System and method to counteract voltage disturbances in open digitline array dynamic random access memory systems Grant 6,836,427 - Vo , et al. December 28, 2	2004-12-28
Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals Grant 6,812,799 - Kirsch November 2, 2	2004-11-02
Trench buried bit line memory devices and methods thereof Grant 6,806,137 - Tran , et al. October 19, 2	2004-10-19
Delay-locked loop circuit and method using a ring oscillator and counter-based delay Grant 6,803,826 - Gomm , et al. October 12, 2	2004-10-12
Method and system for accelerating coupling digital signals App 20040196729 - Kirsch, Howard C.	2004-10-07
System and method to avoid voltage read errors in open digit line array dynamic random access memories App 20040184297 - Kirsch, Howard C.	2004-09-23
Delay-locked loop circuit and method using a ring oscillator and counter-based delay App 20040150445 - Gomm, Tyler J. ; et al.	2004-08-05
Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals App 20040145423 - Kirsch, Howard C.	2004-07-29
Delay-locked loop circuit and method using a ring oscillator and counter-based delay Grant 6,759,911 - Gomm , et al. July 6, 2	2004-07-06
Apparatus and method for a current limiting bleeder device shared by columns of different memory arrays App 20040105333 - Thompson, J. Wayne ; et al.	2004-06-03
Trench buried bit line memory devices and methods thereof App 20040094789 - Tran, Luan C. ; et al.	2004-05-20
Trench Buried Bit Line Memory Devices And Methods Thereof App 20040094786 - Tran, Luan C. ; et al.	2004-05-20
Method and system for accelerating coupling of digital signals Grant 6,738,301 - Kirsch May 18, 2	2004-05-18
Trench buried bit line memory devices Grant 6,734,482 - Tran , et al. May 11, 2	2004-05-11
System and method to avoid voltage read errors in open digit line array dynamic random access memories Grant 6,735,103 - Kirsch May 11, 2	2004-05-11
Synchronous mirror delay (SMD) circuit and method including a ring oscillator for timing coarse and fine delay intervals Grant 6,727,740 - Kirsch April 27, 2	2004-04-27
Synchronous Mirror Delay (smd) Circuit And Method Including A Ring Oscillator For Timing Coarse And Fine Delay Intervals App 20040041606 - Kirsch, Howard C.	2004-03-04
Method And System For Accelerating Coupling Of Digital Signals App 20040042303 - Kirsch, Howard C.	2004-03-04
Method and circuit for reducing DRAM refresh power by reducing access transistor sub threshold leakage App 20040042304 - Kirsch, Howard C.	2004-03-04
System And Method To Avoid Voltage Read Errors In Open Digit Line Array Dynamic Random Access Memories App 20040042242 - Kirsch, Howard C.	2004-03-04
Synchronous Mirror Delay (smd) Circuit And Method Including A Counter And Reduced Size Bi-directional Delay Line App 20030234673 - Kirsch, Howard C.	2003-12-25
System and method to counteract voltage disturbances in open digitline array dynamic random access memory systems App 20030227791 - Vo, Huy T. ; et al.	2003-12-11
Synchronous mirror delay (SMD) circuit and method including a counter and reduced size bi-directional delay line Grant 6,621,316 - Kirsch September 16, 2	2003-09-16
Delay-locked Loop Circuit And Method Using A Ring Oscillator And Counter-based Delay App 20030095009 - Gomm, Tyler J. ; et al.	2003-05-22
Local bit switch decode circuit and method Grant 6,327,215 - Ternullo, Jr. , et al. December 4, 2	2001-12-04
Multiple-bit, current mode data bus Grant 6,300,795 - Kirsch , et al. October 9, 2	2001-10-09
Schmitt trigger input stage Grant 6,091,264 - Kirsch , et al. July 18, 2	2000-07-18
Design for high density memory with relaxed metal pitch Grant 6,057,573 - Kirsch , et al. May 2, 2	2000-05-02
Local word line decoder for memory with 2 MOS devices Grant 5,867,445 - Kirsch , et al. February 2, 1	1999-02-02
Integrated circuit output driver incorporating power distribution noise suppression circuitry Grant 5,786,709 - Kirsch , et al. July 28, 1	1998-07-28
Semiconductor device having a static-random-access memory cell Grant 5,739,564 - Kosa , et al. April 14, 1	1998-04-14
Electrically programmable read-only memory cell Grant 5,616,941 - Roth , et al. April 1, 1	1997-04-01
Process for forming an electrically programmable read-only memory cell Grant 5,543,339 - Roth , et al. August 6, 1	1996-08-06
Method for forming a nonvolatile memory device Grant 5,496,756 - Sharma , et al. March 5, 1	1996-03-05
Three-dimensionally integrated nonvolatile SRAM cell and process Grant 5,488,579 - Sharma , et al. January 30, 1	1996-01-30
Semiconductor device and method of formation Grant 5,445,107 - Roth , et al. August 29, 1	1995-08-29
Ferroelectric memory cell and method of sensing and writing the polarization state thereof Grant 5,432,731 - Kirsch , et al. July 11, 1	1995-07-11
Vertical field-effect transistor and a semiconductor memory cell having the transistor Grant 5,416,736 - Kosa , et al. May 16, 1	1995-05-16
Interconnection structure for conductive layers Grant 5,408,130 - Woo , et al. April 18, 1	1995-04-18
Methods of forming a vertical field-effect transistor and a semiconductor memory cell Grant 5,364,810 - Kosa , et al. November 15, 1	1994-11-15
Self-aligned thin film transistor Grant 5,308,997 - Cooper , et al. May 3, 1	1994-05-03
Method for forming a via structure and semiconductor device having the same Grant 5,286,674 - Roth , et al. February 15, 1	1994-02-15
Method for planarizing a layer of material Grant 5,272,117 - Roth , et al. December 21, 1	1993-12-21
Method for forming a nested surface capacitor Grant 5,266,512 - Kirsch November 30, 1	1993-11-30
Method for forming an interconnection structure for conductive layers Grant 5,262,352 - Woo , et al. November 16, 1	1993-11-16
Method for forming a semiconductor device Grant 5,240,558 - Kawasaki , et al. August 31, 1	1993-08-31
Method for forming isolation regions in a semiconductor device Grant 5,212,110 - Pfiester , et al. May 18, 1	1993-05-18
Semiconductor device process using diffusant penetration and source layers for shallow regions Grant 5,141,895 - Pfiester , et al. August 25, 1	1992-08-25
Process for the formation of elevated source and drain structures in a semiconductor device Grant 5,118,639 - Roth , et al. June 2, 1	1992-06-02
Plural transistor silicon on insulator structure with shared electrodes Grant 5,095,347 - Kirsch March 10, 1	1992-03-10
IGFET gating circuit having reduced electric field degradation Grant 4,704,547 - Kirsch November 3, 1	1987-11-03
Dynamic memory with increased data retention time Grant 4,679,172 - Kirsch , et al. July 7, 1	1987-07-07
Zero standby current TTL to CMOS input buffer Grant 4,672,243 - Kirsch June 9, 1	1987-06-09
Sense amplifier for a dynamic RAM Grant 4,669,063 - Kirsch May 26, 1	1987-05-26
Fast column access memory Grant 4,649,522 - Kirsch March 10, 1	1987-03-10
Integrated circuit having a variably boosted node Grant 4,583,157 - Kirsch , et al. April 15, 1	1986-04-15
Bootstrapped clock driver including delay means Grant 4,472,644 - Kirsch September 18, 1	1984-09-18
MOS Bootstrapped buffer for voltage level conversion with fast output rise time Grant 4,408,136 - Kirsch October 4, 1	1983-10-04
Voltage generator circuitry Grant 4,250,414 - Kirsch February 10, 1	1981-02-10
Dynamic sense-refresh detector amplifier Grant 4,162,416 - Beecham , et al. July 24, 1	1979-07-24
Current control circuit for light emitting diode Grant 4,160,934 - Kirsch July 10, 1	1979-07-10

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