Kirloskar; Mohan
Patent Applications and Registrations
Patent applications and USPTO patent grants for Kirloskar; Mohan.The latest application filed is for "ball grid array package and process for manufacturing same".
- Kirloskar; Mohan - Cupertino CA
| Patent | Date |
|---|---|
| Cavity-type integrated circuit package Grant 7,732,914 - McLellan , et al. June 8, 2 | 2010-06-08 |
| Integrated circuit package with partially exposed contact pads and process for fabricating the same Grant 7,411,289 - McLellan , et al. August 12, 2 | 2008-08-12 |
| Shielded integrated circuit package Grant 7,381,588 - Patel , et al. June 3, 2 | 2008-06-03 |
| Process for fabricating an integrated circuit package with reduced mold warping Grant 7,371,610 - Fan , et al. May 13, 2 | 2008-05-13 |
| Integrated circuit package and method for fabricating same Grant 7,348,663 - Kirloskar , et al. March 25, 2 | 2008-03-25 |
| Integrated circuit package and method for fabricating same Grant 7,344,920 - Kirloskar , et al. March 18, 2 | 2008-03-18 |
| Thermally enhanced cavity-down integrated circuit package Grant 7,342,305 - Diao , et al. March 11, 2 | 2008-03-11 |
| Ball grid array package that includes a collapsible spacer for separating die adapter from a heat spreader Grant 7,315,080 - Fan , et al. January 1, 2 | 2008-01-01 |
| Ball grid array package and process for manufacturing same App 20060223229 - Kirloskar; Mohan ; et al. | 2006-10-05 |
| Integrated circuit package and process for fabricating the same Grant 7,091,581 - McLellan , et al. August 15, 2 | 2006-08-15 |
| Thin leadless plastic chip carrier Grant 7,081,403 - Kirloskar , et al. July 25, 2 | 2006-07-25 |
| Shielded integrated circuit package Grant 7,071,545 - Patel , et al. July 4, 2 | 2006-07-04 |
| Method of fabricating a leadless plastic chip carrier Grant 7,033,517 - Fan , et al. April 25, 2 | 2006-04-25 |
| Thin leadless plastic chip carrier Grant 7,009,286 - Kirloskar , et al. March 7, 2 | 2006-03-07 |
| Ball grid array package and process for manufacturing same Grant 6,987,032 - Fan , et al. January 17, 2 | 2006-01-17 |
| Thermally enhanced cavity-down integrated circuit package Grant 6,984,785 - Diao , et al. January 10, 2 | 2006-01-10 |
| Ball grid array package and process for manufacturing same Grant 6,933,176 - Kirloskar , et al. August 23, 2 | 2005-08-23 |
| High speed wafer sort and final test Grant 6,777,971 - Kirloskar , et al. August 17, 2 | 2004-08-17 |
| High speed wafer sort and final test App 20030214317 - Kirloskar, Mohan ; et al. | 2003-11-20 |
uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.
While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.
All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.
| 