Kirihata; Toshiaki K.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kirihata; Toshiaki K..The latest application filed is for "destructive-read random access memory system buffered with destructive-read memory cache".

Company Profile

0.10.10

Kirihata; Toshiaki K. - Poughkeepsie NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Destructive-read random access memory system buffered with destructive-read memory cache Grant 7,203,794 - Ji , et al. April 10, 2	2007-04-10
System and method for disconnecting a portion of an integrated circuit Grant 7,057,866 - Hsu , et al. June 6, 2	2006-06-06
Destructive-read Random Access Memory System Buffered With Destructive-read Memory Cache App 20050226083 - Ji, Brian L. ; et al.	2005-10-13
Destructive-read random access memory system buffered with destructive-read memory cache Grant 6,948,028 - Ji , et al. September 20, 2	2005-09-20
Method and apparatus for read bitline clamping for gain cell DRAM devices Grant 6,831,866 - Kirihata December 14, 2	2004-12-14
Destructive-read Random Access Memory System Buffered With Destructive-read Memory Cache App 20040221097 - Ji, Brian L. ; et al.	2004-11-04
Destructive-read random access memory system buffered with destructive-read memory cache Grant 6,801,980 - Ji , et al. October 5, 2	2004-10-05
Multiple subarray DRAM having a single shared sense amplifier Grant 6,768,692 - Luk , et al. July 27, 2	2004-07-27
Method and configuration to allow a lower wordline boosted voltage operation while increasing a sensing signal with access transistor threshold voltage Grant 6,751,152 - Hsu , et al. June 15, 2	2004-06-15
Ultra high-speed DDP-SRAM cache Grant 6,751,151 - Hsu , et al. June 15, 2	2004-06-15
Multiple subarray DRAM having a single shared sense amplifier App 20040017691 - Luk, Wing K. ; et al.	2004-01-29
Destructive-read random access memory system buffered with destructive-read memory cache App 20030204667 - Ji, Brian L. ; et al.	2003-10-30
Method and configuration to allow a lower wordline boosted voltage operation while increasing a sensing signal with access transistor threshold voltage App 20030081447 - Hsu, Louis L. ; et al.	2003-05-01
Integrated redundancy architecture system for an embedded DRAM Grant 6,542,973 - Hsu , et al. April 1, 2	2003-04-01
System and method for disconnecting a portion of an integrated circuit App 20030034825 - Hsu, Louis L. ; et al.	2003-02-20
Integrated redundancy architecture system for an embedded dram App 20030009615 - Hsu, Louis L. ; et al.	2003-01-09
Ultra High-speed DDP-SRAM cache App 20020174298 - Hsu, Louis L. ; et al.	2002-11-21
Early write dram architecture with vertically folded bitlines App 20020172067 - Kirihata, Toshiaki K. ; et al.	2002-11-21
System and method for increasing the speed of memories App 20020147883 - Hsu, Louis L. ; et al.	2002-10-10
Floating wordline using a dynamic row decoder and bitline VDD precharge Grant 6,426,914 - Dennard , et al. July 30, 2	2002-07-30

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