| Patent | Date |
|---|
Three-dimensional memory device having epitaxial germanium-containing vertical channel and method of making thereof
Grant 10,121,794 - Gunji-Yoneoka , et al. November 6, 2 | 2018-11-06 |
Method of forming a staircase in a semiconductor device using a linear alignment control feature
Grant 9,985,046 - Lu , et al. May 29, 2 | 2018-05-29 |
Three-dimensional Memory Device Having Epitaxial Germanium-containing Vertical Channel And Method Of Making Thereof
App 20170365613 - GUNJI-YONEOKA; Marika ; et al. | 2017-12-21 |
Method Of Forming A Staircase In A Semiconductor Device Using A Linear Alignmnent Control Feature
App 20170358594 - LU; Zhenyu ; et al. | 2017-12-14 |
Forming 3D memory cells after word line replacement
Grant 9,716,101 - Lu , et al. July 25, 2 | 2017-07-25 |
Memory Hole Last Boxim
App 20160343718 - Lu; Zhenyu ; et al. | 2016-11-24 |
HTO offset for long leffective, better device performance
Grant 9,455,352 - Cheng , et al. September 27, 2 | 2016-09-27 |
Oro and orpro with bit line trench to suppress transport program disturb
Grant 9,245,895 - Cheng , et al. January 26, 2 | 2016-01-26 |
Structures and methods for making NAND flash memory
Grant 9,224,475 - Sel , et al. December 29, 2 | 2015-12-29 |
Hto Offset For Long Leffective, Better Device Performance
App 20140167138 - Cheng; Ning ; et al. | 2014-06-19 |
Structures and Methods for Making NAND Flash Memory
App 20140054669 - Sel; Jongsun ; et al. | 2014-02-27 |
HTO offset for long Leffective, better device performance
Grant 8,653,581 - Cheng , et al. February 18, 2 | 2014-02-18 |
HTO offset and BL trench process for memory device to improve device performance
Grant 8,330,209 - Cheng , et al. December 11, 2 | 2012-12-11 |
Oro And Orpro With Bit Line Trench To Suppress Transport Program Disturb
App 20110278660 - Cheng; Ning ; et al. | 2011-11-17 |
ORO and ORPRO with bit line trench to suppress transport program disturb
Grant 8,012,830 - Cheng , et al. September 6, 2 | 2011-09-06 |
Hto Offset And Bl Trench Process For Memory Device To Improve Device Performance
App 20110169069 - Cheng; Ning ; et al. | 2011-07-14 |
HTO offset spacers and dip off process to define junction
Grant 7,943,983 - Wu , et al. May 17, 2 | 2011-05-17 |
HTO offset and BL trench process for memory device to improve device performance
Grant 7,935,596 - Cheng , et al. May 3, 2 | 2011-05-03 |
Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics
Grant 7,906,807 - Cheng , et al. March 15, 2 | 2011-03-15 |
Use Of A Polymer Spacer And Si Trench In A Bitline Junction Of A Flash Memory Cell To Improve Tpd Characteristics
App 20100264480 - Cheng; Ning ; et al. | 2010-10-21 |
Image Recording Condition Setting Apparatus, Image Recording Condition Setting Method, And Drive Recorder
App 20100208076 - Kinoshita; Hiro | 2010-08-19 |
Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics
Grant 7,776,688 - Cheng , et al. August 17, 2 | 2010-08-17 |
Hto Offset For Long Leffective, Better Device Performance
App 20100155817 - Cheng; Ning ; et al. | 2010-06-24 |
Hto Offset Spacers And Dip Off Process To Define Junction
App 20100155785 - Wu; Huaqiang ; et al. | 2010-06-24 |
Hto Offset And Bl Trench Process For Memory Device To Improve Device Performance
App 20100155816 - Cheng; Ning ; et al. | 2010-06-24 |
Oro And Orpro With Bit Line Trench To Suppress Transport Program Disturb
App 20090039405 - Cheng; Ning ; et al. | 2009-02-12 |
Use Of A Polymer Spacer And Si Trench In A Bitline Junction Of A Flash Memory Cell To Improve Tpd Characteristics
App 20090042378 - Cheng; Ning ; et al. | 2009-02-12 |
| 