Kini; Naveen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kini; Naveen.The latest application filed is for "semiconductor package with dual second level electrical interconnections".

Company Profile

0.7.6

Kini; Naveen - San Jose CA
Kini; Naveen - Fremont CA US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor package with dual second level electrical interconnections Grant 10,028,380 - Tambat , et al. July 17, 2	2018-07-17
Semiconductor Package With Dual Second Level Electrical Interconnections App 20160120031 - Tambat; Abhishek Ramesh ; et al.	2016-04-28
PCB circuit modification from multiple to individual chip enable signals Grant 8,817,511 - McCarthy , et al. August 26, 2	2014-08-26
Electronic component including micro balls Grant 8,637,779 - Upadhyayula , et al. January 28, 2	2014-01-28
Electronic Component Including Micro Balls App 20120305305 - Upadhyayula; Suresh ; et al.	2012-12-06
Vias For Mitigating Pad Delamination App 20120281377 - Kini; Naveen	2012-11-08
Pcb Circuit Modification From Multiple To Individual Chip Enable Signals App 20100309707 - McCarthy; Michael ; et al.	2010-12-09
PCB circuit modification from multiple to individual chip enable signals Grant 7,778,057 - McCarthy , et al. August 17, 2	2010-08-17
Method of making PCB circuit modification from multiple to individual chip enable signals Grant 7,709,278 - McCarthy , et al. May 4, 2	2010-05-04
Method Of Making Pcb Circuit Modification From Multiple To Individual Chip Enable Signals App 20080206904 - McCarthy; Michael ; et al.	2008-08-28
Pcb Circuit Modification From Multiple To Individual Chip Enable Signals App 20080208384 - McCarthy; Michael ; et al.	2008-08-28

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