Kingsley; Christopher H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kingsley; Christopher H..The latest application filed is for "memory management through control of data processing tasks".

Company Profile

8.25.10

Kingsley; Christopher H. - Longmont CO
Kingsley; Christopher H. - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory Management Through Control Of Data Processing Tasks App 20220253338 - Riley; Adam David ; et al.	2022-08-11
Performing hash joins using parallel processing Grant 11,334,524 - Harding, Jr. , et al. May 17, 2	2022-05-17
Error Handling During Asynchronous Processing Of Sequential Data Blocks App 20210303386 - Kingsley; Christopher H. ; et al.	2021-09-30
Error handling during asynchronous processing of sequential data blocks Grant 11,061,754 - Kingsley , et al. July 13, 2	2021-07-13
Memory allocation in a data analytics system Grant 10,996,855 - Harding, Jr. , et al. May 4, 2	2021-05-04
Error Handling During Asynchronous Processing Of Sequential Data Blocks App 20210042179 - Kingsley; Christopher H. ; et al.	2021-02-11
Asynchronously Processing Sequential Data Blocks App 20200142906 - Harding, JR.; Edward P. ; et al.	2020-05-07
Memory Allocation in a Data Analytics System App 20200133504 - Harding, JR.; Edward P. ; et al.	2020-04-30
Performing Hash Joins Using Parallel Processing App 20200050585 - Harding, JR.; Edward P. ; et al.	2020-02-13
Memory allocation in a data analytics system Grant 10,558,364 - Harding, Jr. , et al. Feb	2020-02-11
Asynchronously processing sequential data blocks Grant 10,552,452 - Harding, Jr. , et al. Fe	2020-02-04
Performing hash joins using parallel processing Grant 10,489,348 - Harding, Jr. , et al. Nov	2019-11-26
Memory Allocation In A Data Analytics System App 20190114085 - Harding, JR.; Edward P. ; et al.	2019-04-18
Asynchronously Processing Sequential Data Blocks App 20190114353 - Harding, JR.; Edward P. ; et al.	2019-04-18
Performing Hash Joins Using Parallel Processing App 20190018855 - Harding, JR.; Edward P. ; et al.	2019-01-17
Method Of Data Aggregation For Cache Optimization And Efficient Processing App 20180330288 - Harding, JR.; Edward P. ; et al.	2018-11-15
Scheduling processes in simulation of a circuit design based on simulation costs and runtime states of HDL processes Grant 8,768,678 - Mihalache , et al. July 1, 2	2014-07-01
Multi-threaded deterministic router Grant 8,671,379 - Jain , et al. March 11, 2	2014-03-11
Parallel signal routing Grant 8,386,983 - Kingsley , et al. February 26, 2	2013-02-26
Multi-threaded deterministic router Grant 8,312,409 - Jain , et al. November 13, 2	2012-11-13
Methods of enabling functions of a design to be implemented in an integrated circuit device and a computer program product Grant 8,155,907 - Lesea , et al. April 10, 2	2012-04-10
Multilevel shared database for routing Grant 8,136,075 - Das , et al. March 13, 2	2012-03-13
Automatic isolation of a defect in a programmable logic device Grant 7,795,901 - Yang , et al. September 14, 2	2010-09-14
Compensation for performance variation in integrated circuits Grant 7,765,511 - Perez , et al. July 27, 2	2010-07-27
System for measuring propagation delays Grant 7,482,886 - Kingsley January 27, 2	2009-01-27
Circuit for measuring signal delays of asynchronous inputs of synchronous elements Grant 7,373,560 - Kingsley , et al. May 13, 2	2008-05-13
Tunable clock distribution system for reducing power dissipation Grant 6,882,182 - Conn , et al. April 19, 2	2005-04-19
Method and system for measuring signal propagation delays using ring oscillators Grant 6,219,305 - Patrie , et al. April 17, 2	2001-04-17
System with downstream set or clear for measuring signal propagation delays on integrated circuits Grant 6,075,418 - Kingsley , et al. June 13, 2	2000-06-13
Automated optimization of hierarchical netlists Grant 5,956,257 - Ginetti , et al. September 21, 1	1999-09-21
Method and apparatus for identifying flip-flops in HDL descriptions of circuits without specific templates Grant 5,854,926 - Kingsley , et al. December 29, 1	1998-12-29
Datapath synthesis method and apparatus utilizing a structured cell library Grant 5,519,627 - Mahmood , et al. May 21, 1	1996-05-21
Behavioral synthesis of circuits including high impedance buffers Grant 5,299,137 - Kingsley March 29, 1	1994-03-29

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