Kim; Songmin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kim; Songmin.The latest application filed is for "wide input common mode sense amplifier and its application as an apparatus to accurately measure delay between two discrete time events".

Company Profile

0.13.10

Kim; Songmin - Beaverton OR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Wide input common mode sense amplifier Grant 7,429,881 - Deng , et al. September 30, 2	2008-09-30
On-die offset reference circuit block Grant 7,417,459 - Wilson , et al. August 26, 2	2008-08-26
Method for configurably enabling pulse clock generation for multiple signaling modes Grant 7,276,942 - Cole , et al. October 2, 2	2007-10-02
Wide input common mode sense amplifier and its application as an apparatus to accurately measure delay between two discrete time events App 20070159215 - Deng; Chaodan ; et al.	2007-07-12
Adjusting input output timing App 20070157049 - Kim; Songmin ; et al.	2007-07-05
Global I/O timing adjustment using calibrated delay elements Grant 7,197,659 - Lim , et al. March 27, 2	2007-03-27
On-die offset reference circuit block App 20060239051 - Wilson; Timothy M. ; et al.	2006-10-26
Method for configurably enabling pulse clock generation for multiple signaling modes App 20060139068 - Cole; Ying ; et al.	2006-06-29
Closed-loop independent DLL-controlled rise/fall time control circuit Grant 7,038,513 - Wilson , et al. May 2, 2	2006-05-02
Closed-loop independent DLL-controlled rise/fall time control circuit Grant 7,038,512 - Wilson , et al. May 2, 2	2006-05-02
Configurable enabling pulse clock generation for multiple signaling modes Grant 7,038,505 - Cole , et al. May 2, 2	2006-05-02
Closed-loop independent DLL-controlled rise/fall time control circuit App 20050285647 - Wilson, Timothy M. ; et al.	2005-12-29
Closed-loop independent DLL-controlled rise/fall time control circuit App 20050285648 - Wilson, Timothy M. ; et al.	2005-12-29
Configurable enabling pulse clock generation for multiple signaling modes App 20050141666 - Cole, Ying ; et al.	2005-06-30
Clocking an I/O buffer, having a selectable phase difference from the system clock, to and from a remote I/O buffer clocked in phase with the system clock Grant 6,748,549 - Chao , et al. June 8, 2	2004-06-08
Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation Grant 6,717,455 - Mughal , et al. April 6, 2	2004-04-06
Apparatus and method of use a single reference component in a master-slave configuration for multiple circuit compensation App 20030094991 - Mughal, Usman A. ; et al.	2003-05-22
Global I/O timing adjustment using calibrated delay elements App 20030065962 - Lim, Chee How ; et al.	2003-04-03
Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation Grant 6,535,047 - Mughal , et al. March 18, 2	2003-03-18
Apparatus and method to use a single reference component in a master-slave configuration for multiple circuit compensation App 20020171466 - Mughal, Usman A. ; et al.	2002-11-21
Apparatus and method for linear on-die termination in an open drain bus architecture system Grant 6,424,170 - Raman , et al. July 23, 2	2002-07-23
Apparatus and method for dynamic on-die termination in an open-drain bus architecture system Grant 6,411,122 - Mughal , et al. June 25, 2	2002-06-25
Self-configurable clock input buffer compatible with high-voltage single-ended and low-voltage differential clock signals Grant 6,407,591 - Wong , et al. June 18, 2	2002-06-18

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