Kim; Sarah E.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kim; Sarah E..The latest application filed is for "three-dimensional stacked substrate arrangements".

Company Profile

0.45.55

Kim; Sarah E. - Portland OR US
Kim; Sarah E. - Seoul KR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Three-dimensional stacked substrate arrangements Grant 8,421,225 - Ramanathan , et al. April 16, 2	2013-04-16
Three-dimensional Stacked Substrate Arrangements App 20120280387 - Ramanathan; Shriram ; et al.	2012-11-08
Three-dimensional stacked substrate arrangements Grant 8,203,208 - Ramanathan , et al. June 19, 2	2012-06-19
Three-dimensional Stacked Substrate Arrangements App 20110260319 - Ramanathan; Shriram ; et al.	2011-10-27
Three-dimensional stacked substrate arrangements Grant 7,973,407 - Ramanathan , et al. July 5, 2	2011-07-05
Cooling micro-channels Grant 7,842,553 - Kim , et al. November 30, 2	2010-11-30
Integrated re-combiner for electroosmotic pumps using porous frits Grant 7,723,208 - Kim , et al. May 25, 2	2010-05-25
Method of forming a stack of heat generating integrated circuit chips with intervening cooling integrated circuit chips Grant 7,696,015 - Kim , et al. April 13, 2	2010-04-13
Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack Grant 7,615,462 - Kim , et al. November 10, 2	2009-11-10
Using external radiators with electroosmotic pumps for cooling integrated circuits Grant 7,576,432 - Kim , et al. August 18, 2	2009-08-18
Three-dimensional stacked substrate arrangements App 20090174070 - Ramanathan; Shriram ; et al.	2009-07-09
Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same Grant 7,537,954 - Ramanathan , et al. May 26, 2	2009-05-26
3D integrated circuits using thick metal for backside connections and offset bumps Grant 7,410,884 - Ramanathan , et al. August 12, 2	2008-08-12
Method and structure for interfacing electronic devices Grant 7,348,217 - Kobrinsky , et al. March 25, 2	2008-03-25
Packaged electroosmotic pumps using porous frits for cooling integrated circuits App 20070278668 - Kim; Sarah E. ; et al.	2007-12-06
Packaged electroosmotic pumps using porous frits for cooling integrated circuits Grant 7,274,106 - Kim , et al. September 25, 2	2007-09-25
Capacitor with insulating nanostructure Grant 7,271,434 - Kellar , et al. September 18, 2	2007-09-18
Capacitor with conducting nanostructure Grant 7,265,406 - Kellar , et al. September 4, 2	2007-09-04
Cooling micro-channels App 20070200226 - Kim; Sarah E. ; et al.	2007-08-30
Methods of Processing Thick ILD Layers Using Spray Coating or Lamination for C4 Wafer Level Thick Metal Integrated Flow App 20070190776 - Kim; Sarah E. ; et al.	2007-08-16
Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode Grant 7,244,983 - Kim , et al. July 17, 2	2007-07-17
Cooling micro-channels Grant 7,227,257 - Kim , et al. June 5, 2	2007-06-05
3D integrated circuits using thick metal for backside connections and offset bumps App 20070117348 - Ramanathan; Shriram ; et al.	2007-05-24
Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices App 20070111386 - Kim; Sarah E. ; et al.	2007-05-17
Method And Structure For Vertically-stacked Device Contact App 20070087528 - Kim; Sarah E. ; et al.	2007-04-19
Method and apparatus for low temperature copper to copper bonding Grant 7,183,648 - Ramanathan , et al. February 27, 2	2007-02-27
Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack App 20070020805 - Kim; Sarah E. ; et al.	2007-01-25
Method and structure for interfacing electronic devices App 20070015340 - Kobrinsky; Mauro J. ; et al.	2007-01-18
Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices Grant 7,157,787 - Kim , et al. January 2, 2	2007-01-02
Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack Grant 7,148,565 - Kim , et al. December 12, 2	2006-12-12
Electroosmotic pumps using porous frits for cooling integrated circuit stacks App 20060226541 - Kim; Sarah E. ; et al.	2006-10-12
Self-aligned electrodes contained within the trenches of an electroosmotic pump Grant 7,105,382 - Myers , et al. September 12, 2	2006-09-12
Differential planarization Grant 7,105,925 - Boardman , et al. September 12, 2	2006-09-12
Ultra-high capacitance device based on nanostructures Grant 7,091,084 - Kellar , et al. August 15, 2	2006-08-15
Electroosmotic pumps using porous frits for cooling integrated circuit stacks Grant 7,084,495 - Kim , et al. August 1, 2	2006-08-01
Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack Grant 7,056,807 - Kellar , et al. June 6, 2	2006-06-06
Methods of forming backside connections on a wafer stack Grant 7,056,813 - Morrow , et al. June 6, 2	2006-06-06
Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same App 20060097383 - Ramanathan; Shriram ; et al.	2006-05-11
Wafer bonding using a flexible bladder press for three dimensional (3D) vertical stack integration Grant 7,037,804 - Kellar , et al. May 2, 2	2006-05-02
Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same Grant 7,034,394 - Ramanathan , et al. April 25, 2	2006-04-25
Thick metal layer integrated process flow to improve power delivery and mechanical buffering App 20060076678 - Kim; Sarah E. ; et al.	2006-04-13
Using external radiators with electroosmotic pumps for cooling integrated circuits App 20060055030 - Kim; Sarah E. ; et al.	2006-03-16
Using external radiators with electroosmotic pumps for cooling integrated circuits Grant 6,992,381 - Kim , et al. January 31, 2	2006-01-31
Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow App 20060012039 - Kim; Sarah E. ; et al.	2006-01-19
Electro-osmotic pumps and micro-channels Grant 6,981,849 - Kim , et al. January 3, 2	2006-01-03
Thick metal layer integrated process flow to improve power delivery and mechanical buffering Grant 6,977,435 - Kim , et al. December 20, 2	2005-12-20
Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof Grant 6,975,016 - Kellar , et al. December 13, 2	2005-12-13
Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow Grant 6,943,440 - Kim , et al. September 13, 2	2005-09-13
Capacitor with conducting nanostructure App 20050194628 - Kellar, Scot A. ; et al.	2005-09-08
Method and structure for interfacing electronic devices App 20050184400 - Kobrinsky, Mauro J. ; et al.	2005-08-25
Differential planarization App 20050170759 - Boardman, James A. ; et al.	2005-08-04
Methods of forming backside connections on a wafer stack App 20050164490 - Morrow, Patrick ; et al.	2005-07-28
Ultra-high capacitance device based on nanostructures App 20050151261 - Kellar, Scot A. ; et al.	2005-07-14
Differential planarization Grant 6,914,002 - Boardman , et al. July 5, 2	2005-07-05
Ultra-high capacitance device based on nanostructures Grant 6,911,373 - Kellar , et al. June 28, 2	2005-06-28
Etch thinning techniques for wafer-to-wafer vertical stacks Grant 6,908,565 - Kim , et al. June 21, 2	2005-06-21
Self-aligned electrodes contained within the trenches of an electroosmotic pump App 20050112816 - Myers, Alan M. ; et al.	2005-05-26
Methods of forming backside connections on a wafer stack Grant 6,897,125 - Morrow , et al. May 24, 2	2005-05-24
Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode App 20050101099 - Kim, Sarah E. ; et al.	2005-05-12
Using external radiators with electroosmotic pumps for cooling integrated circuits App 20050093138 - Kim, Sarah E. ; et al.	2005-05-05
Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same Grant 6,887,769 - Kellar , et al. May 3, 2	2005-05-03
Electroosmotic pumps using porous frits for cooling integrated circuit stacks App 20050085018 - Kim, Sarah E. ; et al.	2005-04-21
Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same App 20050077619 - Ramanathan, Shriram ; et al.	2005-04-14
Integrated re-combiner for electroosmotic pumps using porous frits App 20050074953 - Kim, Sarah E. ; et al.	2005-04-07
Packaged electroosmotic pumps using porous frits for cooling integrated circuits App 20050062150 - Kim, Sarah E. ; et al.	2005-03-24
Method and structure for interfacing electronic devices Grant 6,870,270 - Kobrinsky , et al. March 22, 2	2005-03-22
Methods Of Forming Backside Connections On A Wafer Stack App 20050059217 - Morrow, Patrick ; et al.	2005-03-17
Thick metal layer integrated process flow to improve power delivery and mechanical buffering App 20050051894 - Kim, Sarah E. ; et al.	2005-03-10
Methods of processing thick ILD layers using spray coating or lamination for C4 wafer level thick metal integrated flow App 20050051904 - Kim, Sarah E. ; et al.	2005-03-10
Three-dimensional stacked substrate arrangements App 20050003650 - Ramanathan, Shriram ; et al.	2005-01-06
Method and apparatus for low temperature copper to copper bonding App 20050003652 - Ramanathan, Shriram ; et al.	2005-01-06
Method and apparatus for low temperature copper to copper bonding App 20050003664 - Ramanathan, Shriram ; et al.	2005-01-06
Method and structure for interfacing electronic devices App 20040232537 - Kobrinsky, Mauro J. ; et al.	2004-11-25
Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices App 20040219763 - Kim, Sarah E. ; et al.	2004-11-04
Thinning techniques for wafer-to-wafer vertical stacks Grant 6,790,748 - Kim , et al. September 14, 2	2004-09-14
Fabrication of 3-D capacitor with dual damascene process Grant 6,790,780 - Kim , et al. September 14, 2	2004-09-14
Cooling micro-channels App 20040145047 - Kim, Sarah E. ; et al.	2004-07-29
Wafer bonding for three-dimensional (3D) integration App 20040142540 - Kellar, Scot A. ; et al.	2004-07-22
Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices Grant 6,762,076 - Kim , et al. July 13, 2	2004-07-13
Ultra-high capacitance device based on nanostructures App 20040131774 - Kellar, Scot A. ; et al.	2004-07-08
Differential planarization App 20040127049 - Boardman, James A. ; et al.	2004-07-01
Method and structure for vertically-stacked device contact App 20040124509 - Kim, Sarah E. ; et al.	2004-07-01
Thinning techniques for wafer-to-wafer vertical stacks App 20040121556 - Kim, Sarah E. ; et al.	2004-06-24
Electro-osmotic pumps and micro-channels App 20040120827 - Kim, Sarah E. ; et al.	2004-06-24
Etch thinning techniques for wafer-to-wafer vertical stacks App 20040118806 - Kim, Sarah E. ; et al.	2004-06-24
Arrangements having increased on-die capacitance App 20040092072 - Kim, Sarah E.	2004-05-13
Ultra-high capacitance device based on nanostructures App 20040058504 - Kellar, Scot A. ; et al.	2004-03-25
Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack App 20040014308 - Kellar, Scot A. ; et al.	2004-01-22
Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack Grant 6,661,085 - Kellar , et al. December 9, 2	2003-12-09
Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack Grant 6,645,832 - Kim , et al. November 11, 2	2003-11-11
Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack App 20030205824 - Kim, Sarah E. ; et al.	2003-11-06
Etch Stop Layer For Silicon (si) Via Etch In Three-dimensional (3-d) Wafer-to-wafer Vertical Stack App 20030157796 - Kim, Sarah E. ; et al.	2003-08-21
Dielectric recess for wafer-to-wafer and die-to-die metal bonding and method of fabricating the same App 20030157782 - Kellar, Scot A. ; et al.	2003-08-21
Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices App 20030157748 - Kim, Sarah E. ; et al.	2003-08-21
Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack App 20030148590 - Kellar, Scot A. ; et al.	2003-08-07
Wafer bonding for three-dimensional (3D) integration App 20030148596 - Kellar, Scot A. ; et al.	2003-08-07
Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode Grant 6,599,808 - Kim , et al. July 29, 2	2003-07-29
Method and device for on-chip decoupling capacitor using nanostructures as bottom electrode App 20030064583 - Kim, Sarah E. ; et al.	2003-04-03
Fabrication of 3-D capacitor with dual damascene process App 20030060052 - Kim, Sarah E. ; et al.	2003-03-27