Kim; Ryoung-han

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kim; Ryoung-han.The latest application filed is for "integration of finfet device".

Company Profile

2.28.26

Kim; Ryoung-han - Plano TX
Kim; Ryoung-han - San Jose CA
Kim; Ryoung-Han - Clifton Park NY US
Kim; Ryoung-Han - Albany NY
Kim; Ryoung-han - Guilderland NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Integration of finFET device Grant 10,950,488 - Kim , et al. March 16, 2	2021-03-16
Integration Of Finfet Device App 20190273013 - KIM; Ryoung-han ; et al.	2019-09-05
Design And Integration Of Finfet Device App 20180108564 - KIM; Ryoung-han ; et al.	2018-04-19
Design And Integration Of Finfet Device App 20150171217 - KIM; Ryoung-han ; et al.	2015-06-18
Method of printing multiple structure widths using spacer double patterning Grant 9,029,263 - Kim , et al. May 12, 2	2015-05-12
Method of forming semiconductor device with multiple level patterning Grant 8,815,748 - Wallow , et al. August 26, 2	2014-08-26
Optical polarizer with nanotube array Grant 8,792,161 - LaFontaine , et al. July 29, 2	2014-07-29
Multilayer interconnect structure and method for integrated circuits Grant 8,664,113 - Kim March 4, 2	2014-03-04
Spacer lithography Grant 8,642,474 - Kim , et al. February 4, 2	2014-02-04
Multilayer Interconnect Structure And Method For Integrated Circuits App 20130313725 - Kim; Ryoung-Han	2013-11-28
Method for forming a high resolution resist pattern on a semiconductor wafer Grant 8,586,269 - Okoroanyanwu , et al. November 19, 2	2013-11-19
Spacer double patterning that prints multiple CD in front-end-of-line Grant 8,450,833 - Kim May 28, 2	2013-05-28
Double exposure technology using high etching selectivity Grant 8,445,182 - Kim , et al. May 21, 2	2013-05-21
Method for forming an interconnect structure Grant 8,435,884 - Kim , et al. May 7, 2	2013-05-07
Methods of Forming a Non-Planar Cap Layer Above Conductive Lines on a Semiconductor Device App 20130043589 - Kim; Ryoung-Han ; et al.	2013-02-21
Methods for fabricating semiconductor devices Grant 8,303,831 - Kim November 6, 2	2012-11-06
Multilayer Interconnect Structure And Method For Integrated Circuits App 20120273958 - KIM; Ryoung-Han	2012-11-01
Method of forming semiconductor device Grant 8,236,592 - Kim , et al. August 7, 2	2012-08-07
Method For Forming An Interconnect Structure App 20120058640 - Kim; Ryoung-Han ; et al.	2012-03-08
Spacer Double Patterning That Prints Multiple Cd In Front-end-of-line App 20120043646 - Kim; Ryoung-han	2012-02-23
In-die focus monitoring with binary mask Grant 8,009,274 - Kim August 30, 2	2011-08-30
Methods For Fabricating Semiconductor Devices App 20110014790 - KIM; Ryoung-Han	2011-01-20
Stabilization of deep ultraviolet photoresist Grant 7,851,136 - Levinson , et al. December 14, 2	2010-12-14
Multiple exposure technique using OPC to correct distortion Grant 7,829,266 - Deng , et al. November 9, 2	2010-11-09
Double Exposure Technology Using High Etching Selectivity App 20100270652 - Kim; Ryoung-Han ; et al.	2010-10-28
EUV pellicle and method for fabricating semiconductor dies using same Grant 7,767,985 - Okoroanyanwu , et al. August 3, 2	2010-08-03
EUV pellicle with increased EUV light transmittance Grant 7,723,704 - Wood, II , et al. May 25, 2	2010-05-25
Inverse self-aligned spacer lithography Grant 7,718,529 - Deng , et al. May 18, 2	2010-05-18
Double exposure technology using high etching selectivity Grant 7,704,680 - Kim , et al. April 27, 2	2010-04-27
EUV debris mitigation filter and method for fabricating semiconductor dies using same Grant 7,663,127 - Wood, II , et al. February 16, 2	2010-02-16
In-die Focus Monitoring With Binary Mask App 20100002214 - Kim; Ryoung-han	2010-01-07
Multiple Exposure Technique Using Opc To Correct Distortion App 20090040483 - Deng; Yunfei ; et al.	2009-02-12
Inverse Self-aligned Spacer Lithography App 20090023298 - Deng; Yunfei ; et al.	2009-01-22
Spacer Lithography App 20090017628 - KIM; Ryoung-han ; et al.	2009-01-15
High Fidelity Multiple Resist Patterning App 20080292991 - Wallow; Thomas I. ; et al.	2008-11-27
EUV diffractive optical element for semiconductor wafer lithography and method for making same App 20080259458 - LaFontaine; Bruno M. ; et al.	2008-10-23
Method for forming a high resolution resist pattern on a semiconductor wafer App 20080233494 - Okoroanyanwu; Uzodinma ; et al.	2008-09-25
EUV debris mitigation filter and method for fabricating semiconductor dies using same App 20080225245 - Wood; Obert Reeves ; et al.	2008-09-18
Optical polarizer with nanotube array App 20080198453 - LaFontaine; Bruno M. ; et al.	2008-08-21
Method Of Forming Semiconductor Device With Multiple Level Patterning App 20080171447 - Wallow; Thomas Ingolf ; et al.	2008-07-17
Method Of Forming Semiconductor Device App 20080171446 - Kim; Ryoung-han ; et al.	2008-07-17
EUV pellicle and method for fabricating semiconductor dies using same App 20080152873 - Okoroanyanwu; Uzodinma ; et al.	2008-06-26
EUV pellicle with increased EUV light transmittance App 20080113491 - Wood; Obert Reeves ; et al.	2008-05-15
Double exposure technology using high etching selectivity App 20070287101 - Kim; Ryoung-Han ; et al.	2007-12-13
Stabilization Of Deep Ultraviolet Photoresist App 20070281248 - Levinson; Harry J. ; et al.	2007-12-06

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