Kim; Ryan Ryoung han

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kim; Ryan Ryoung han.The latest application filed is for "method for forming a via hole self-aligned with a metal block on a substrate".

Company Profile

5.40.36

Kim; Ryan Ryoung han - Bertem BE
Kim; Ryan Ryoung-Han - Albany NY
Kim; Ryan Ryoung han - Berterm BE
Kim; Ryan Ryoung-Han - Clifton Park NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for forming a via hole self-aligned with a metal block on a substrate Grant 11,270,912 - O'Toole , et al. March 8, 2	2022-03-08
Mask for extreme-ultraviolet (extreme-UV) lithography and method for manufacturing the same Grant 11,092,884 - Lee , et al. August 17, 2	2021-08-17
Method for Forming a Via Hole Self-aligned with a Metal Block on a Substrate App 20210183698 - O'Toole; Martin ; et al.	2021-06-17
Method for producing a gate cut structure on an array of semiconductor fins Grant 10,978,335 - Chan , et al. April 13, 2	2021-04-13
Method for analyzing design of an integrated circuit Grant 10,592,632 - Kim , et al.	2020-03-17
Method for Producing a Gate Cut Structure on an Array of Semiconductor Fins App 20200083090 - Chan; Boon Teik ; et al.	2020-03-12
Vertical transistor static random access memory cell Grant 10,580,779 - Lim , et al.	2020-03-03
Vertical Transistor Static Random Access Memory Cell App 20190267387 - Lim; Kwan-Yong ; et al.	2019-08-29
Mask for Extreme-Ultraviolet (Extreme-UV) Lithography and Method for Manufacturing the Same App 20190155138 - Lee; Jae Uk ; et al.	2019-05-23
Dummy gate used as interconnection and method of making the same Grant 10,283,505 - Wang , et al.	2019-05-07
Method of utilizing trench silicide in a gate cross-couple construct Grant 10,192,792 - Kim Ja	2019-01-29
Shrink process aware assist features Grant 10,153,162 - Kim , et al. Dec	2018-12-11
Methods for forming conductive paths and vias Grant 10,147,637 - Drissi , et al. De	2018-12-04
Method for Analyzing Design of an Integrated Circuit App 20180307792 - Kim; Ryan Ryoung han ; et al.	2018-10-25
Method of utilizing trench silicide in a gate cross-couple construct Grant 10,103,066 - Kim October 16, 2	2018-10-16
Methods For Forming Conductive Paths And Vias App 20180261497 - Drissi; Youssef ; et al.	2018-09-13
Semiconductor device configured for avoiding electrical shorting Grant 10,050,118 - Xie , et al. August 14, 2	2018-08-14
Method of making self-aligned continuity cuts in mandrel and non-mandrel metal lines Grant 9,953,834 - Sun , et al. April 24, 2	2018-04-24
Shrink Process Aware Assist Features App 20180096839 - KIM; Ryan Ryoung-Han ; et al.	2018-04-05
Single and double diffusion breaks on integrated circuit products comprised of FinFET devices Grant 9,865,704 - Xie , et al. January 9, 2	2018-01-09
Method of making self-aligned continuity cuts in mandrel and non-mandrel metal lines Grant 9,859,120 - Sun , et al. January 2, 2	2018-01-02
Method, Apparatus And System For Fabricating Self-aligned Contact Using Block-type Hard Mask App 20170358585 - Lim; Kwanyong ; et al.	2017-12-14
Vertical channel transistor-based semiconductor memory structure Grant 9,711,511 - Lim , et al. July 18, 2	2017-07-18
Single And Double Diffusion Breaks On Integrated Circuit Products Comprised Of Finfet Devices App 20170141211 - Xie; Ruilong ; et al.	2017-05-18
Dummy Gate Used As Interconnection And Method Of Making The Same App 20170141110 - WANG; Wenhui ; et al.	2017-05-18
Methods for optical proximity correction in the design and fabrication of integrated circuits using extreme ultraviolet lithography Grant 9,651,855 - Sun , et al. May 16, 2	2017-05-16
Dummy gate used as interconnection and method of making the same Grant 9,595,478 - Wang , et al. March 14, 2	2017-03-14
Methods of forming reduced resistance local interconnect structures and the resulting devices Grant 9,553,028 - Xie , et al. January 24, 2	2017-01-24
Methods of forming products with FinFET semiconductor devices without removing fins in certain areas of the product Grant 9,543,416 - Sung , et al. January 10, 2	2017-01-10
Dummy Gate Used As Interconnection And Method Of Making The Same App 20160365288 - WANG; Wenhui ; et al.	2016-12-15
Gate Contact Structure Having Gate Contact Layer App 20160336399 - LABONTE; Andre ; et al.	2016-11-17
Gate contact structure having gate contact layer Grant 9,490,317 - Labonte , et al. November 8, 2	2016-11-08
Method for producing self-aligned vias Grant 9,484,258 - Kim , et al. November 1, 2	2016-11-01
SAV using selective SAQP/SADP Grant 9,478,462 - Wang , et al. October 25, 2	2016-10-25
Metal segments as landing pads and local interconnects in an IC device Grant 9,466,604 - Woo , et al. October 11, 2	2016-10-11
Method Of Utilizing Trench Silicide In A Gate Cross-couple Construct App 20160293495 - KIM; Ryan Ryoung-han	2016-10-06
Method Of Utilizing Trench Silicide In A Gate Cross-couple Construct App 20160293496 - KIM; Ryan Ryoung-han	2016-10-06
Methods of forming features having differing pitch spacing and critical dimensions Grant 9,449,835 - Jang , et al. September 20, 2	2016-09-20
Methods of forming integrated circuits and multiple critical dimension self-aligned double patterning processes Grant 9,431,264 - Jang , et al. August 30, 2	2016-08-30
Methods of forming single and double diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products Grant 9,412,616 - Xie , et al. August 9, 2	2016-08-09
Merged source/drain and gate contacts in SRAM bitcell Grant 9,406,616 - Woo , et al. August 2, 2	2016-08-02
Method of utilizing trench silicide in a gate cross-couple construct Grant 9,379,027 - Kim June 28, 2	2016-06-28
Methods For Optical Proximity Correction In The Design And Fabrication Of Integrated Circuits Using Extreme Ultraviolet Lithography App 20160162624 - Sun; Lei ; et al.	2016-06-09
Methods Of Forming Diffusion Breaks On Integrated Circuit Products Comprised Of Finfet Devices And The Resulting Products App 20160163604 - Xie; Ruilong ; et al.	2016-06-09
Merged Source/drain And Gate Contacts In Sram Bitcell App 20160163644 - WOO; Youngtag ; et al.	2016-06-09
Methods Of Forming Features Having Differing Pitch Spacing And Critical Dimensions App 20160163555 - Jang; Linus ; et al.	2016-06-09
Methods of forming diffusion breaks on integrated circuit products comprised of FinFET devices and the resulting products Grant 9,362,181 - Xie , et al. June 7, 2	2016-06-07
Buried fin contact structures on FinFET semiconductor devices Grant 9,362,403 - Xie , et al. June 7, 2	2016-06-07
Contact formation for semiconductor device Grant 9,362,279 - Xie , et al. June 7, 2	2016-06-07
Metal Segments As Landing Pads And Local Interconnects In An Ic Device App 20160141291 - WOO; Youngtag ; et al.	2016-05-19
Methods Of Forming Products With Finfet Semiconductor Devices Without Removing Fins In Certain Areas Of The Product App 20160133726 - Sung; Min Gyu ; et al.	2016-05-12
Method Of Utilizing Trench Silicide In A Gate Cross-couple Construct App 20160111341 - KIM; Ryan Ryoung-han	2016-04-21
Semiconductor devices with contact structures and a gate structure positioned in trenches formed in a layer of material Grant 9,299,781 - Xie , et al. March 29, 2	2016-03-29
Finfet Semiconductor Devices With Stressed Layers App 20160043223 - Xie; Ruilong ; et al.	2016-02-11
Methods for fabricating integrated circuits including selectively forming and removing fin structures Grant 9,209,037 - Cantone , et al. December 8, 2	2015-12-08
Methods for fabricating integrated circuits using self-aligned quadruple patterning Grant 9,209,038 - Cantone , et al. December 8, 2	2015-12-08
Semiconductor Devices With A Layer Of Material Having A Plurality Of Source/drain Trenches App 20150349053 - Xie; Ruilong ; et al.	2015-12-03
Methods of forming stressed layers on FinFET semiconductor devices and the resulting devices Grant 9,202,918 - Xie , et al. December 1, 2	2015-12-01
Buried fin contact structures on FinFET semiconductor devices App 20150340452 - Xie; Ruilong ; et al.	2015-11-26
Methods of forming FinFET devices in different regions of an integrated circuit product Grant 9,184,169 - Kim , et al. November 10, 2	2015-11-10
Methods For Fabricating Integrated Circuits Using Self-aligned Quadruple Patterning App 20150318181 - Cantone; Jason Richard ; et al.	2015-11-05
Vertical Transistor Static Random Access Memory Cell App 20150318288 - Lim; Kwan-Yong ; et al.	2015-11-05
Semiconductor Device Configured For Avoiding Electrical Shorting App 20150318345 - XIE; Ruilong ; et al.	2015-11-05
Methods of forming semiconductor devices using a layer of material having a plurality of trenches formed therein Grant 9,171,934 - Xie , et al. October 27, 2	2015-10-27
Methods for fabricating integrated circuits using self-aligned quadruple patterning Grant 9,171,764 - Kim , et al. October 27, 2	2015-10-27
Methods Of Forming Finfet Devices In Different Regions Of An Integrated Circuit Product App 20150294976 - Kim; Ryan Ryoung-Han ; et al.	2015-10-15
Methods of forming contact structures on finfet semiconductor devices and the resulting devices Grant 9,153,694 - Xie , et al. October 6, 2	2015-10-06
Methods Of Forming Semiconductor Devices Using A Layer Of Material Having A Plurality Of Trenches Formed Therein App 20150279972 - Xie; Ruilong ; et al.	2015-10-01
Semiconductor Devices With Contact Structures And A Gate Structure Positioned In Trenches Formed In A Layer Of Material App 20150279935 - Xie; Ruilong ; et al.	2015-10-01
Methods Of Forming Reduced Resistance Local Interconnect Structures And The Resulting Devices App 20150270176 - Xie; Ruilong ; et al.	2015-09-24
Methods For Fabricating Integrated Circuits Including Selectively Forming And Removing Fin Structures App 20150255299 - Cantone; Jason Richard ; et al.	2015-09-10
Methods For Fabricating Integrated Circuits Using Self-aligned Quadruple Patterning App 20150170973 - Kim; Ryan Ryoung Han ; et al.	2015-06-18
Methods Of Forming Stressed Layers On Finfet Semiconductor Devices And The Resulting Devices App 20150076609 - Xie; Ruilong ; et al.	2015-03-19
Methods Of Forming Contact Structures On Finfet Semiconductor Devices And The Resulting Devices App 20150060960 - Xie; Ruilong ; et al.	2015-03-05
Methods Of Forming Integrated Circuits And Multiple Critical Dimension Self-aligned Double Patterning Processes App 20150064912 - Jang; Linus ; et al.	2015-03-05
Multilayer interconnect structure and method for integrated circuits Grant 8,796,859 - Kim August 5, 2	2014-08-05

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