| Patent | Date |
|---|
Stacked silicon package assembly having thermal management
Grant 11,355,412 - Gandhi , et al. June 7, 2 | 2022-06-07 |
Integrated circuit device with stacked dies having mirrored circuitry
Grant 11,205,639 - Kim , et al. December 21, 2 | 2021-12-21 |
Multi-die device structures and methods
Grant 11,114,360 - Gandhi , et al. September 7, 2 | 2021-09-07 |
IC die with dummy structures
Grant 11,114,344 - Lin , et al. September 7, 2 | 2021-09-07 |
Integrated Circuit Device With Stacked Dies Having Mirrored Circuitry
App 20210265312 - KIM; Myongseob ; et al. | 2021-08-26 |
Test circuits for testing a die stack
Grant 11,054,461 - Chong , et al. July 6, 2 | 2021-07-06 |
Package Integration For Memory Devices
App 20200303341 - Kim; Myongseob ; et al. | 2020-09-24 |
Package integration for memory devices
Grant 10,770,430 - Kim , et al. Sep | 2020-09-08 |
Chip package assembly with modular core dice
Grant 10,692,837 - Kim , et al. | 2020-06-23 |
Stacked Silicon Package Assembly Having Thermal Management
App 20200105642 - Gandhi; Jaspreet Singh ; et al. | 2020-04-02 |
Methods and apparatus for thermal interface material (TIM) bond line thickness (BLT) reduction and TIM adhesion enhancement for efficient thermal management
Grant 10,529,645 - Gandhi , et al. J | 2020-01-07 |
Wafer edge partial die engineered for stacked die yield
Grant 10,431,565 - Kim , et al. O | 2019-10-01 |
Circuit for and method of testing bond connections between a first die and a second die
Grant 10,262,911 - Gong , et al. | 2019-04-16 |
Methods And Apparatus For Thermal Interface Material (tim) Bond Line Thickness (blt) Reduction And Tim Adhesion Enhancement For Efficient Thermal Management
App 20180358280 - Gandhi; Jaspreet Singh ; et al. | 2018-12-13 |
Shielded wire arrangement for die testing
Grant 9,412,674 - Kim , et al. August 9, 2 | 2016-08-09 |
Method and apparatus for tracking interposer dies in a silicon stacked interconnect technology (SSIT) product
Grant 9,236,367 - Chen , et al. January 12, 2 | 2016-01-12 |
Method and apparatus for tracking interposer dies in a silicon stacked interconnect technology (SSIT) product
Grant 8,987,009 - Chen , et al. March 24, 2 | 2015-03-24 |
Method of testing a semiconductor structure
Grant 8,810,269 - Gong , et al. August 19, 2 | 2014-08-19 |
Methods of manufacturing a semiconductor structure
Grant 8,802,454 - Rahman , et al. August 12, 2 | 2014-08-12 |
Method Of Testing A Semiconductor Structure
App 20140091819 - Gong; Yuqing ; et al. | 2014-04-03 |
Memory structure having SRAM cells and SONOS devices
Grant 8,542,514 - Lakshminarayanan , et al. September 24, 2 | 2013-09-24 |
Semiconductor device and method for making the same
Grant 8,329,568 - Ahn , et al. December 11, 2 | 2012-12-11 |
Transistor with floating gate and electret
Grant 7,960,776 - Kim , et al. June 14, 2 | 2011-06-14 |
Transistor With Floating Gate And Electret
App 20080094074 - Kim; Myongseob ; et al. | 2008-04-24 |
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