loadpatents
name:-0.017361879348755
name:-0.013038873672485
name:-0.00047397613525391
Kim; Kee Sup Patent Filings

Kim; Kee Sup

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kim; Kee Sup.The latest application filed is for "logic yield learning vehicle with phased design windows".

Company Profile
0.13.16
  • Kim; Kee Sup - El Dorado Hills CA
  • Kim; Kee Sup - Hwaseong-si KR
  • Kim; Kee Sup - Folsom CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Logic yield learning vehicle with phased design windows
Grant 11,403,452 - Kim August 2, 2
2022-08-02
Logic Yield Learning Vehicle With Phased Design Windows
App 20170109470 - Kim; Kee Sup
2017-04-20
Integrated circuit having main route and detour route for signal transmission and integrated circuit package including the same
Grant 9,524,922 - Lim , et al. December 20, 2
2016-12-20
System on chip and temperature control method thereof
Grant 9,459,680 - Kim , et al. October 4, 2
2016-10-04
Integrated Circuit Having Main Route And Detour Route For Signal Transmission And Integrated Circuit Package Including The Same
App 20150371926 - LIM; Kyounghwan ;   et al.
2015-12-24
System On Chip And Temperature Control Method Thereof
App 20140032949 - KIM; Hyungock ;   et al.
2014-01-30
Method of designing a system-on-chip including a tapless standard cell, designing system and system-on-chip
Grant 8,522,188 - Kim , et al. August 27, 2
2013-08-27
Method Of Designing A System-on-chip Including A Tapless Standard Cell, Designing System And System-on-chip
App 20130185692 - KIM; Hyung-Ock ;   et al.
2013-07-18
Method Of Generating Standard Cell Library For Dpl Process And Methods Of Producing A Dpl Mask And Circuit Pattern Using The Same
App 20130086536 - KIM; WOOK ;   et al.
2013-04-04
Hierarchical test response compaction for a plurality of logic blocks
Grant 7,818,642 - Kim , et al. October 19, 2
2010-10-19
Compacting circuit responses
Grant 7,814,383 - Mitra , et al. October 12, 2
2010-10-12
Compacting circuit responses
Grant 7,574,640 - Mitra , et al. August 11, 2
2009-08-11
System and shadow bistable circuits coupled to output joining circuit
Grant 7,523,371 - Mitra , et al. April 21, 2
2009-04-21
Hierarchical test response compaction for a plurality of logic blocks
App 20090083599 - Kim; Kee Sup ;   et al.
2009-03-26
System and shadow circuits with output joining circuit
Grant 7,278,074 - Mitra , et al. October 2, 2
2007-10-02
Stimulus generation
Grant 7,240,260 - Mitra , et al. July 3, 2
2007-07-03
Compacting circuit responses
Grant 7,185,253 - Mitra , et al. February 27, 2
2007-02-27
System and shadow circuits with output joining circuit
App 20060168489 - Mitra; Subhasish ;   et al.
2006-07-27
Compacting circuit responses
App 20060036985 - Mitra; Subhasish ;   et al.
2006-02-16
System and shadow bistable circuits coupled to output joining circuit
App 20060015786 - Mitra; Subhasish ;   et al.
2006-01-19
At speed testing asynchronous signals
Grant 6,918,074 - Kim , et al. July 12, 2
2005-07-12
Compacting circuit responses
App 20050055613 - Mitra, Subhasish ;   et al.
2005-03-10
Stimulus generation
App 20040117703 - Mitra, Subhasish ;   et al.
2004-06-17
At speed testing of asynchronous signals
App 20040003332 - Kim, Kee Sup ;   et al.
2004-01-01
Compacting circuit responses
App 20030188269 - Mitra, Subhasish ;   et al.
2003-10-02

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