| Patent | Date |
|---|
Wiring structures and semiconductor devices
Grant 10,229,876 - Kim , et al. | 2019-03-12 |
Wiring structure and method of forming the same, and semiconductor device including the wiring structure
Grant 9,716,043 - Park , et al. July 25, 2 | 2017-07-25 |
Wiring Structure And Method Of Forming The Same, And Semiconductor Device Including The Wiring Structure
App 20160379891 - PARK; JIN-HYEUNG ; et al. | 2016-12-29 |
Wiring Structures And Semiconductor Devices
App 20160343660 - KIM; Jun-Jung ; et al. | 2016-11-24 |
Organic light emitting display device and method for fabricating the same
Grant 8,865,486 - Kim , et al. October 21, 2 | 2014-10-21 |
Organic Light Emitting Display Device And Method For Fabricating The Same
App 20140227810 - KIM; Jun-Jung ; et al. | 2014-08-14 |
Organic light emitting display device and method for fabricating the same
Grant 8,742,436 - Kim , et al. June 3, 2 | 2014-06-03 |
Organic Light Emitting Display Device And Method For Fabricating The Same
App 20130082288 - KIM; Jun-Jung ; et al. | 2013-04-04 |
Integrated circuit system employing stress-engineered spacers
Grant 8,338,245 - Lee , et al. December 25, 2 | 2012-12-25 |
Method of fabricating semiconductor integrated circuit device
Grant 8,227,308 - Lim , et al. July 24, 2 | 2012-07-24 |
Field Effect Transistors Having Gate Electrode Silicide Layers with Reduced Surface Damage
App 20110156110 - Kim; Jun-jung ; et al. | 2011-06-30 |
Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon
Grant 7,923,365 - Kim , et al. April 12, 2 | 2011-04-12 |
Methods of forming integrated circuit devices having ion-cured electrically insulating layers therein
Grant 7,838,390 - Kim , et al. November 23, 2 | 2010-11-23 |
Methods for removing gate sidewall spacers in CMOS semiconductor fabrication processes
Grant 7,790,622 - Lee , et al. September 7, 2 | 2010-09-07 |
Dual stress memory technique method and related structure
Grant 7,785,950 - Fang , et al. August 31, 2 | 2010-08-31 |
Method Of Fabricating Semiconductor Integrated Circuit Device
App 20100167533 - Lim; Ha-Jin ; et al. | 2010-07-01 |
Overlapped stressed liners for improved contacts
Grant 7,612,414 - Chen , et al. November 3, 2 | 2009-11-03 |
Non-conformal stress liner for enhanced MOSFET performance
Grant 7,585,773 - Fang , et al. September 8, 2 | 2009-09-08 |
Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques
Grant 7,541,288 - Kim , et al. June 2, 2 | 2009-06-02 |
Methods of Forming Field Effect Transistors Having Stress-Inducing Sidewall Insulating Spacers Thereon and Devices Formed Thereby
App 20090101979 - Kim; Jun-jung ; et al. | 2009-04-23 |
Methods of Forming Integrated Circuit Devices Having Ion-Cured Electrically Insulating Layers Therein
App 20090098706 - Kim; Jun-jung ; et al. | 2009-04-16 |
Pre-silicide spacer removal
Grant 7,504,309 - Dyer , et al. March 17, 2 | 2009-03-17 |
Strained Semiconductor Device and Method of Making Same
App 20090050972 - Lindsay; Richard ; et al. | 2009-02-26 |
Dual Stress Liners For Integrated Circuits
App 20090014807 - TANG; Teck Jung ; et al. | 2009-01-15 |
Overlapped Stressed Liners For Improved Contacts
App 20080237737 - Chen; Xiangdong ; et al. | 2008-10-02 |
Methods of Forming Integrated Circuit Structures Using Insulator Deposition and Insulator Gap Filling Techniques
App 20080220584 - Kim; Jun-jung ; et al. | 2008-09-11 |
Integrated Circuit System Employing Stress-engineered Spacers
App 20080173934 - Lee; Jae Gon ; et al. | 2008-07-24 |
Integrated Circuit System Having Strained Transistor
App 20080142897 - Teh; Young Way ; et al. | 2008-06-19 |
Non-conformal Stress Liner For Enhanced Mosfet Performance
App 20080122003 - Fang; Sunfei ; et al. | 2008-05-29 |
Pre-silicide spacer removal
App 20080090412 - Dyer; Thomas W. ; et al. | 2008-04-17 |
Semiconductor Device Having a Dual Stress Liner and Light Exposure Apparatus for Forming the Dual Stress Liner
App 20080029823 - Park; Jae-Eon ; et al. | 2008-02-07 |
Methods of fabricating semiconductor devices having a dual stress liner
Grant 7,297,584 - Park , et al. November 20, 2 | 2007-11-20 |
Dual Stress Memory Technique Method And Related Structure
App 20070105299 - Fang; Sunfei ; et al. | 2007-05-10 |
Semiconductor device having a dual stress liner, method of manufacturing the semiconductor device and light exposure apparatus for forming the dual stress liner
App 20070082439 - Park; Jae-Eon ; et al. | 2007-04-12 |
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