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name:-0.0096220970153809
name:-0.019952058792114
name:-0.0016450881958008
Kim; Hung-Eil Patent Filings

Kim; Hung-Eil

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kim; Hung-Eil.The latest application filed is for "method and apparatus for optimizing an optical proximity correction model".

Company Profile
0.17.7
  • Kim; Hung-Eil - San Jose CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method of forming an electronic device including forming features within a mask and a selective removal process
Grant 8,003,545 - Lukanc , et al. August 23, 2
2011-08-23
Method and apparatus for optimizing an optical proximity correction model
Grant 7,788,609 - Kim , et al. August 31, 2
2010-08-31
System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques
Grant 7,657,864 - Tabery , et al. February 2, 2
2010-02-02
Method And Apparatus For Optimizing An Optical Proximity Correction Model
App 20090249261 - KIM; HUNG-EIL ;   et al.
2009-10-01
Method Of Forming An Electronic Device Including Forming Features Within A Mask And A Selective Removal Process
App 20090209107 - Lukanc; Todd ;   et al.
2009-08-20
System and method for designing an integrated circuit device
Grant 7,543,256 - Lukanc , et al. June 2, 2
2009-06-02
Method of forming narrowly spaced flash memory contact openings and lithography masks
Grant 7,507,661 - Lingunis , et al. March 24, 2
2009-03-24
Mask CD measurement monitor outside of the pellicle area
Grant 7,422,828 - Kim September 9, 2
2008-09-09
System and method for fabricating contact holes
Grant 7,384,725 - Minvielle , et al. June 10, 2
2008-06-10
Two mask photoresist exposure pattern for dense and isolated regions
Grant 7,368,225 - Subramanian , et al. May 6, 2
2008-05-06
Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin
Grant 7,313,769 - Lukanc , et al. December 25, 2
2007-12-25
System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques
Grant 7,269,804 - Tabery , et al. September 11, 2
2007-09-11
System And Method For Integrated Circuit Device Design And Manufacture Using Optical Rule Checking To Screen Resolution Enhancement Techniques
App 20070209030 - Tabery; Cyrus E. ;   et al.
2007-09-06
Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results
Grant 7,207,017 - Tabery , et al. April 17, 2
2007-04-17
System and method for design rule creation and selection
Grant 7,194,725 - Lukanc , et al. March 20, 2
2007-03-20
Method of verifying an optical proximity correction (OPC) model
Grant 7,065,738 - Kim June 20, 2
2006-06-20
Patterning for elongated V.sub.SS contact flash memory
Grant 7,018,922 - Kim , et al. March 28, 2
2006-03-28
Method of forming narrowly spaced flash memory contact openings and lithography masks
App 20060035459 - Lingunis; Emmanuil H. ;   et al.
2006-02-16
System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques
App 20050229125 - Tabery, Cyrus E. ;   et al.
2005-10-13
System and method for fabricating contact holes
App 20050221233 - Minvielle, Anna M. ;   et al.
2005-10-06
Patterning for elliptical Vss contact on flash memory
Grant 6,900,124 - Kim , et al. May 31, 2
2005-05-31
Method and system for determining flow rates for contact formation
Grant 6,811,932 - Kim November 2, 2
2004-11-02
Accurate contact critical dimension measurement using variable threshold method
Grant 6,581,023 - Kim June 17, 2
2003-06-17
Dark field trench in an alternating phase shift mask to avoid phase conflict
App 20020160275 - Kim, Hung-Eil
2002-10-31

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