Kikuda; Shigeru

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kikuda; Shigeru.The latest application filed is for "semiconductor device capable of shortening test time and suppressing increase in chip area, and method of manufacturing semiconductor integrated circuit device".

Company Profile

0.13.0

Kikuda; Shigeru - Hyogo JP
Kikuda; Shigeru - Kikuchi-gun JP
Kikuda; Shigeru - Hyogo-ken JP

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Semiconductor device capable of shortening test time and suppressing increase in chip area, and method of manufacturing semiconductor integrated circuit device Grant 6,962,827 - Furue , et al. November 8, 2	2005-11-08
Semiconductor device with improved noise resistivity Grant 6,166,415 - Sakemi , et al. December 26, 2	2000-12-26
Liquid crystal display apparatus with shorting ring Grant 5,767,929 - Yachi , et al. June 16, 1	1998-06-16
Semiconductor memory device permitting high speed data transfer and high density integration Grant 5,586,076 - Miyamoto , et al. December 17, 1	1996-12-17
Redundancy circuit for repairing defective bits in semiconductor memory device Grant 5,574,729 - Kinoshita , et al. November 12, 1	1996-11-12
Semiconductor memory device comprising a test circuit and a method of operation thereof Grant 5,384,784 - Mori , et al. January 24, 1	1995-01-24
Semiconductor integrated circuit device including a plurality of cell array blocks Grant 5,357,478 - Kikuda , et al. October 18, 1	1994-10-18
Semiconductor memory device having multiple memory arrays and including redundancy circuit for repairing a faulty bit Grant 5,323,348 - Mori , et al. June 21, 1	1994-06-21
Semiconductor memory device including a redundancy circuitry for repairing a defective memory cell and a method for repairing a defective memory cell Grant 5,146,429 - Kawai , et al. September 8, 1	1992-09-08
Delay circuit employing different threshold FET's Grant 5,063,313 - Kikuda , et al. November 5, 1	1991-11-05
Semiconductor integrated circuit device Grant 4,994,689 - Kikuda , et al. February 19, 1	1991-02-19
MIS transistor driven inverter circuit capable of individually controlling rising portion and falling portion of output waveform Grant 4,931,668 - Kikuda , et al. June 5, 1	1990-06-05
Delay circuit Grant 4,914,326 - Kikuda , et al. April 3, 1	1990-04-03

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