Kieslich; Albrecht

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kieslich; Albrecht.The latest application filed is for "method for producing an optoelectronic semiconductor chip, and optoelectronic semiconductor chip".

Company Profile

0.10.12

Kieslich; Albrecht - Radebeul DE
Kieslich; Albrecht - Radebuel DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method For Producing An Optoelectronic Semiconductor Chip, And Optoelectronic Semiconductor Chip App 20210126163 - Huber; Michael ; et al.	2021-04-29
Method of producing a plurality of optoelectronic semiconductor chips, and optoelectronic semiconductor chip Grant 9,825,198 - Rode , et al. November 21, 2	2017-11-21
Method Of Producing A Plurality Of Optoelectronic Semiconductor Chips, And Optoelectronic Semiconductor Chip App 20140319547 - Rode; Patrick ; et al.	2014-10-30
Method for fabricating a semiconductor structure Grant 7,259,060 - Amon , et al. August 21, 2	2007-08-21
Method for fabricating a semiconductor product with a memory area and a logic area Grant 7,217,610 - Graf , et al. May 15, 2	2007-05-15
Method for fabricating a trench structure which is electrically connected to a substrate on one side via a buried contact Grant 7,189,614 - Kudelka , et al. March 13, 2	2007-03-13
Method for transferring a layout of an integrated circuit level to a semiconductor substrate App 20050196689 - Nolscher, Christoph ; et al.	2005-09-08
Method for fabricating a semiconductor structure App 20050124124 - Amon, Jurgen ; et al.	2005-06-09
Compact semiconductor structure Grant 6,864,170 - Hohnsdorf , et al. March 8, 2	2005-03-08
Method for fabricating a trench structure which is electrically connected to a substrate on one side via a buried contact App 20050032324 - Kudelka, Stephan ; et al.	2005-02-10
Mask for fabricating semiconductor components Grant 6,849,364 - Kieslich , et al. February 1, 2	2005-02-01
Method for fabricating a semiconductor product with a memory area and a logic area App 20040259298 - Graf, Werner ; et al.	2004-12-23
Method for planarizing an isolating layer Grant 6,753,236 - Feldner , et al. June 22, 2	2004-06-22
Method of forming a bitline and a bitline contact, and dynamic memory cell including a bitline and bitline made contact according to the method Grant 6,750,112 - Kieslich June 15, 2	2004-06-15
Stacked via with specially designed landing pad for integrated semiconductor structures Grant 6,737,748 - Bauch , et al. May 18, 2	2004-05-18
Compact semiconductor structure and method for producing the same App 20040029374 - Hohnsdorf, Falko ; et al.	2004-02-12
Method for producing an insulation Grant 6,638,814 - Kieslich , et al. October 28, 2	2003-10-28
Method for planarizing an isolating layer App 20030045105 - Feldner, Klaus ; et al.	2003-03-06
Mask for fabricating semiconductor components App 20030039899 - Kieslich, Albrecht ; et al.	2003-02-27
Method of forming a bitline and a bitline contact, and dynamic memory cell including a bitline and bitline made contact according to the method App 20030002359 - Kieslich, Albrecht	2003-01-02
Stacked via with specially designed landing pad for integrated semiconductor structures App 20020117759 - Bauch, Lothar ; et al.	2002-08-29
Method for manufacturing a field effect transistor App 20020039819 - Curello, Guiseppe ; et al.	2002-04-04

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