loadpatents
name:-0.016596794128418
name:-0.011880159378052
name:-0.00041007995605469
Kieser; Sabine Patent Filings

Kieser; Sabine

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kieser; Sabine.The latest application filed is for "semiconductor memory".

Company Profile
0.9.12
  • Kieser; Sabine - Schliersee DE
  • Kieser; Sabine - Hausham DE
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Semiconductor memory having tri-state driver device
Grant 7,203,102 - Brox , et al. April 10, 2
2007-04-10
Method and device for data transfer
Grant 7,120,818 - Dietrich , et al. October 10, 2
2006-10-10
Semiconductor memory
App 20060087896 - Brox; Martin ;   et al.
2006-04-27
Integrated memory, and a method of operating an integrated memory
Grant 6,882,554 - Markert , et al. April 19, 2
2005-04-19
Latency time circuit for an S-DRAM
Grant 6,819,624 - Acharya , et al. November 16, 2
2004-11-16
Latency time switch for an S-DRAM
Grant 6,804,165 - Schrogmeier , et al. October 12, 2
2004-10-12
DDR memory and storage method
Grant 6,731,567 - Acharya , et al. May 4, 2
2004-05-04
Control circuit for an S-DRAM
Grant 6,717,886 - Pramod , et al. April 6, 2
2004-04-06
Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits
Grant 6,670,802 - Dietrich , et al. December 30, 2
2003-12-30
Latency time switch for an S-DRAM
App 20030218921 - Schrogmeier, Peter ;   et al.
2003-11-27
Latency Time Circuit For An S-dram
App 20030174550 - Acharya, Pramod ;   et al.
2003-09-18
Circuit configuration with a memory array
Grant 6,614,700 - Dietrich , et al. September 2, 2
2003-09-02
Control circuit for an S-DRAM
App 20030161210 - Acharya, Pramod ;   et al.
2003-08-28
DDR memory and storage method
App 20030151971 - Acharya, Pramod ;   et al.
2003-08-14
Integrated memory, and a method of operating an integrated memory
App 20030107910 - Markert, Michael ;   et al.
2003-06-12
Circuit configuration with a memory array
App 20020145923 - Dietrich, Stefan ;   et al.
2002-10-10
Integrated memory having a row access controller for activating and deactivating row lines
App 20020141279 - Dietrich, Stefan ;   et al.
2002-10-03
Method and device for data transfer
App 20020136243 - Dietrich, Stefan ;   et al.
2002-09-26
Integrated circuit having a test operating mode and method for testing a multiplicity of such circuits
App 20020133750 - Dietrich, Stefan ;   et al.
2002-09-19
Circuit configuration for programming a delay in a signal path
App 20020079925 - Dietrich, Stefan ;   et al.
2002-06-27
Voltage pump with switch-on control
App 20020075707 - Dietrich, Stefan ;   et al.
2002-06-20

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