loadpatents
name:-0.0078630447387695
name:-0.007033109664917
name:-0.00046014785766602
Khullar; Shray Patent Filings

Khullar; Shray

Patent Applications and Registrations

Patent applications and USPTO patent grants for Khullar; Shray.The latest application filed is for "scan compression architecture for highly compressed designs and associated methods".

Company Profile
0.7.6
  • Khullar; Shray - New Delhi IN
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Scan compression architecture for highly compressed designs and associated methods
Grant 10,354,742 - Bahl , et al. July 16, 2
2019-07-16
Scan Compression Architecture For Highly Compressed Designs And Associated Methods
App 20170140838 - Bahl; Swapnil ;   et al.
2017-05-18
Scan compression architecture for highly compressed designs and associated methods
Grant 9,606,180 - Bahl , et al. March 28, 2
2017-03-28
Synchronous on-chip clock controllers
Grant 9,264,049 - Bahl , et al. February 16, 2
2016-02-16
Monitoring on-chip clock control during integrated circuit testing
Grant 9,234,938 - Khullar , et al. January 12, 2
2016-01-12
Scan Compression Architecture For Highly Compressed Designs And Associated Methods
App 20150323593 - BAHL; Swapnil ;   et al.
2015-11-12
Monitoring On-chip Clock Control During Integrated Circuit Testing
App 20150323594 - KHULLAR; Shray ;   et al.
2015-11-12
Synchronous On-chip Clock Controllers
App 20150137862 - Bahl; Swapnil ;   et al.
2015-05-21
Integrated circuit with reduced power consumption in a test mode, and related methods
Grant 8,917,123 - Bahl , et al. December 23, 2
2014-12-23
Integrated Circuit With Reduced Power Consumption In A Test Mode, And Related Methods
App 20140292385 - BAHL; SWAPNIL ;   et al.
2014-10-02
Sequential on-chip clock controller with dynamic bypass for multi-clock domain testing
Grant 8,775,857 - Khullar , et al. July 8, 2
2014-07-08
Sequential On-chip Clock Controller With Dynamic Bypass For Multi-clock Domain Testing
App 20120166860 - Khullar; Shray ;   et al.
2012-06-28

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