Khor; Choon Wei
Patent Applications and Registrations
Patent applications and USPTO patent grants for Khor; Choon Wei.The latest application filed is for "hiding instruction cache miss latency by running tag lookups ahead of the instruction accesses".
- Khor; Choon Wei - Sungai Dua N/A MY
- Khor; Choon Wei - Gelugor MY
| Patent | Date |
|---|---|
| Multi-level tracking of in-use state of cache lines Grant 9,348,591 - Kim , et al. May 24, 2 | 2016-05-24 |
| Hiding instruction cache miss latency by running tag lookups ahead of the instruction accesses Grant 9,158,696 - Kim , et al. October 13, 2 | 2015-10-13 |
| Hiding Instruction Cache Miss Latency By Running Tag Lookups Ahead Of The Instruction Accesses App 20140229677 - Kim; Ilhyun ; et al. | 2014-08-14 |
| Multi-level Tracking Of In-use State Of Cache Lines App 20130275733 - Kim; Ilhyun ; et al. | 2013-10-17 |
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