Khare; Mukesh V.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Khare; Mukesh V..The latest application filed is for "cmos structure and method for fabrication thereof using multiple crystallographic orientations and gate materials".

Company Profile

0.12.8

Khare; Mukesh V. - White Plains NY US
Khare; Mukesh V. - Wappingers Falls NY US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials Grant 8,785,281 - Chen , et al. July 22, 2	2014-07-22
High-K metal gate CMOS Grant 8,507,992 - Mo , et al. August 13, 2	2013-08-13
Cmos Structure And Method For Fabrication Thereof Using Multiple Crystallographic Orientations And Gate Materials App 20120142181 - Chen; Tze-Chiang ; et al.	2012-06-07
Protecting exposed metal gate structures from etching processes in integrated circuit manufacturing Grant 8,193,099 - Khare , et al. June 5, 2	2012-06-05
CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials Grant 8,158,481 - Chen , et al. April 17, 2	2012-04-17
High-k Metal Gate Cmos App 20110156158 - Mo; Renee T. ; et al.	2011-06-30
High-K metal gate CMOS Grant 7,943,460 - Mo , et al. May 17, 2	2011-05-17
High-K Metal Gate CMOS App 20100264495 - Mo; Renee T. ; et al.	2010-10-21
Cmos Structure And Method For Fabrication Thereof Using Multiple Crystallographic Orientations And Gate Materials App 20100112800 - Chen; Tze-Chiang ; et al.	2010-05-06
CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials Grant 7,671,421 - Chen , et al. March 2, 2	2010-03-02
CMOS structure and method for fabrication thereof using multiple crystallographic orientations and gate materials App 20070278586 - Chen; Tze-Chiang ; et al.	2007-12-06
Nitrided ultra thin gate dielectrics Grant 7,109,559 - Khare , et al. September 19, 2	2006-09-19
Method for improved plasma nitridation of ultra thin gate dielectrics Grant 6,893,979 - Khare , et al. May 17, 2	2005-05-17
Nitrided ultrathin gate dielectrics App 20050087822 - Khare, Mukesh V. ; et al.	2005-04-28
Use of disposable spacer to introduce gettering in SOI layer Grant 6,635,517 - Chen , et al. October 21, 2	2003-10-21
Use of disposable spacer to introduce gettering in SOI layer App 20030032251 - Chen, Tze-Chiang ; et al.	2003-02-13
Method for improved plasma nitridation of ultra thin gate dielectrics App 20020130377 - Khare, Mukesh V. ; et al.	2002-09-19
Low programming voltage anti-fuse Grant 6,096,580 - Iyer , et al. August 1, 2	2000-08-01

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.