loadpatents
Patent applications and USPTO patent grants for Khanna; Namerita.The latest application filed is for "processing configuration data frames".
Patent | Date |
---|---|
Processing configuration data frames Grant 7,774,682 - Goel , et al. August 10, 2 | 2010-08-10 |
Programmable logic devices Grant 7,606,969 - Aggarwal , et al. October 20, 2 | 2009-10-20 |
Processing Configuration Data Frames App 20080215935 - Goel; Ashish Kumar ;   et al. | 2008-09-04 |
Method and apparatus of reloading erroneous configuration data frames during configuration of programmable logic devices Grant 7,350,134 - Goel , et al. March 25, 2 | 2008-03-25 |
Architecture for programmable logic device Grant 7,154,299 - Swami , et al. December 26, 2 | 2006-12-26 |
Programmable logic devices providing reduced power consumption Grant 7,109,749 - Khanna , et al. September 19, 2 | 2006-09-19 |
High performance interconnect architecture for field programmable gate arrays Grant 7,030,648 - Bal , et al. April 18, 2 | 2006-04-18 |
Programmable logic devices App 20050172070 - Aggarwal, Davinder ;   et al. | 2005-08-04 |
Low power clock distribution scheme Grant 6,879,185 - Swami , et al. April 12, 2 | 2005-04-12 |
High performance interconnect architecture for field programmable gate arrays App 20040178821 - Bal, Ankur ;   et al. | 2004-09-16 |
Method and apparatus of reloading erroneous configuration data frames during configuration of programmable logic devices App 20040153923 - Goel, Ashish Kumar ;   et al. | 2004-08-05 |
Programmable logic devices providing reduced power consumption App 20040008055 - Khanna, Namerita ;   et al. | 2004-01-15 |
Low power clock distribution scheme App 20030218480 - Swami, Parvesh ;   et al. | 2003-11-27 |
Architecture for programmable logic device App 20030214321 - Swami, Parvesh ;   et al. | 2003-11-20 |
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