Khandekar; Viren

Patent Applications and Registrations

Patent applications and USPTO patent grants for Khandekar; Viren.The latest application filed is for "three-dimensional chip-to-wafer integration".

Company Profile

2.24.15

Khandekar; Viren - Flower Mound TX
Khandekar; Viren - Chandler AZ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System for monitoring and controlling an integrated circuit testing machine Grant 11,428,735 - Mijares , et al. August 30, 2	2022-08-30
Wafer-level chip-scale package device having bump assemblies configured to maintain standoff height Grant 10,804,233 - Khandekar , et al. October 13, 2	2020-10-13
Wafer level package device formed using a wafer level lead frame on a carrier wafer having a similar coefficient of thermal expansion as an active wafer Grant 10,304,758 - Thambidurai , et al.	2019-05-28
Three-dimensional chip-to-wafer integration Grant 10,032,749 - Kelkar , et al. July 24, 2	2018-07-24
Wafer-level chip-scale package device having bump assemblies configured to furnish shock absorber functionality Grant 9,721,912 - Khandekar , et al. August 1, 2	2017-08-01
Solder fatigue arrest for wafer level package Grant 9,583,425 - Xu , et al. February 28, 2	2017-02-28
Technique for wafer-level processing of QFN packages Grant 9,472,451 - Khandekar , et al. October 18, 2	2016-10-18
Low-cost low-profile solder bump process for enabling ultra-thin wafer-level packaging (WLP) packages Grant 9,425,064 - Thambidurai , et al. August 23, 2	2016-08-23
Wafer-level passive device integration Grant 9,324,687 - Kelkar , et al. April 26, 2	2016-04-26
Three-dimensional Chip-to-wafer Integration App 20160071826 - Kelkar; Amit S. ; et al.	2016-03-10
Multi-die, high current wafer level package Grant 9,230,903 - Samoilov , et al. January 5, 2	2016-01-05
Wafer-level package device having high-standoff peripheral solder bumps Grant 9,219,043 - Kelkar , et al. December 22, 2	2015-12-22
Three-dimensional chip-to-wafer integration Grant 9,190,391 - Kelkar , et al. November 17, 2	2015-11-17
Multi-die, High Current Wafer Level Package App 20150325512 - Samoilov; Arkadii V. ; et al.	2015-11-12
Integrated circuit device having extended under ball metallization Grant 9,093,333 - Xu , et al. July 28, 2	2015-07-28
Multi-die, high current wafer level package Grant 9,087,779 - Samoilov , et al. July 21, 2	2015-07-21
Wafer-level package device having solder bump assemblies that include an inner pillar structure Grant 9,087,732 - Xu , et al. July 21, 2	2015-07-21
Techniques for wafer-level processing of QFN packages Grant 9,040,408 - Zhou , et al. May 26, 2	2015-05-26
Technique For Wafer-level Processing Of Qfn Packages App 20150028475 - Khandekar; Viren ; et al.	2015-01-29
Wafer-level Chip-scale Package Device Having Bump Assemblies Configured To Furnish Shock Absorber Functionality App 20150008576 - Khandekar; Viren ; et al.	2015-01-08
Techniques for wafer-level processing of QFN packages Grant 8,860,222 - Khandekar , et al. October 14, 2	2014-10-14
Wafer-level Package Device Having High-standoff Peripheral Solder Bumps App 20140264845 - Kelkar; Amit S. ; et al.	2014-09-18
Wafer-level Package Mitigated Undercut App 20140252571 - Khandekar; Viren ; et al.	2014-09-11
Multi-die, High Current Wafer Level Package App 20140183747 - Samoilov; Arkadii V. ; et al.	2014-07-03
Low-cost Low-profile Solder Bump Process For Enabling Ultra-thin Wafer-level Packaging (wlp) Packages App 20140167252 - Thambidurai; Karthik ; et al.	2014-06-19
Solder Fatigue Arrest For Wafer Level Package App 20140131859 - Xu; Yong Li ; et al.	2014-05-15
Wafer-level package device having solder bump assemblies that include an inner pillar structure Grant 8,643,150 - Xu , et al. February 4, 2	2014-02-04
Integrated circuit device having extended under ball metallization Grant 8,575,493 - Xu , et al. November 5, 2	2013-11-05
Techniques For Wafer-level Processing Of Qfn Packages App 20130161817 - Khandekar; Viren ; et al.	2013-06-27
Three-dimensional Chip-to-wafer Integration App 20130105966 - Kelkar; Amit Subhash ; et al.	2013-05-02
Redistribution layer enhancement to improve reliability of wafer level packaging Grant 8,084,871 - Rahim , et al. December 27, 2	2011-12-27
Wafer Level Packaging With Heat Dissipation App 20110233756 - KHANDEKAR; VIREN ; et al.	2011-09-29
Redistribution Layer Enhancement To Improve Reliability Of Wafer Level Packaging App 20110108981 - RAHIM; KAYSAR ; et al.	2011-05-12
Self Alignment Features For An Electronic Assembly App 20070020911 - Khandekar; Viren ; et al.	2007-01-25

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