Khandekar; Narendra S.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Khandekar; Narendra S..The latest application filed is for "memory buffer device integrating refresh".

Company Profile

0.11.7

Khandekar; Narendra S. - Folsom CA
Khandekar, Narendra S. - Bangalore IN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Memory buffer device integrating refresh logic Grant 7,353,329 - Ellis , et al. April 1, 2	2008-04-01
Memory bus termination with memory unit having termination control Grant 6,981,089 - Dodd , et al. December 27, 2	2005-12-27
Apparatus and method to track command signal occurrence for DRAM data transfer Grant 6,976,121 - Khandekar , et al. December 13, 2	2005-12-13
Apparatus and method to track flag transitions for DRAM data transfer Grant 6,976,120 - Khandekar , et al. December 13, 2	2005-12-13
Memory buffer device integrating refresh App 20050071543 - Ellis, Robert M. ; et al.	2005-03-31
Method of addressing individual memory devices on a memory module Grant 6,832,177 - Khandekar , et al. December 14, 2	2004-12-14
Apparatus and method for encoding auto-precharge Grant 6,829,184 - Khandekar , et al. December 7, 2	2004-12-07
Method of addressing individual memory devices on a memory module App 20040128429 - Khandekar, Narendra S. ; et al.	2004-07-01
Memory buffer arrangement Grant 6,639,820 - Khandekar , et al. October 28, 2	2003-10-28
Apparatus and method to track flag transitions for DRAM data transfer App 20030145156 - Khandekar, Narendra S. ; et al.	2003-07-31
Apparatus and method to track command signal occurrence for dram data transfer App 20030145161 - Khandekar, Narendra S. ; et al.	2003-07-31
Apparatus and method for encoding auto-precharge App 20030142557 - Khandekar, Narendra S. ; et al.	2003-07-31
Method and apparatus for resource sharing in a multi-processor system App 20030140189 - Bogin, Zohar ; et al.	2003-07-24
Memory bus termination with memory unit having termination control App 20030126338 - Dodd, James M. ; et al.	2003-07-03
Method and apparatus for resource sharing in a multi-processor system Grant 6,502,150 - Bogin , et al. December 31, 2	2002-12-31
AGP read and CPU wire coherency Grant 6,157,397 - Bogin , et al. December 5, 2	2000-12-05
Method and apparatus for controlling data transfer between a synchronous DRAM-type memory and a system bus Grant 5,926,828 - Khandekar July 20, 1	1999-07-20
Method for parallel processing of dram read request in a memory-cache controller system Grant 5,873,119 - Khandekar , et al. February 16, 1	1999-02-16

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.