Khan; Anisul H.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Khan; Anisul H..The latest application filed is for "component for semiconductor process chamber having surface treatment to reduce particle emission".

Company Profile

0.12.17

Khan; Anisul H. - Santa Clara CA
Khan; Anisul H - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method of matching two or more plasma reactors Grant 9,305,748 - Saraf , et al. April 5, 2	2016-04-05
Component For Semiconductor Process Chamber Having Surface Treatment To Reduce Particle Emission App 20160056059 - SUN; Jennifer ; et al.	2016-02-25
Predictive method of matching two plasma reactors Grant 9,184,021 - Saraf , et al. November 10, 2	2015-11-10
Predictive Method Of Matching Two Plasma Reactors App 20150099314 - Saraf; Gaurav ; et al.	2015-04-09
Method Of Matching Two Or More Plasma Reactors App 20150096959 - Saraf; Gaurav ; et al.	2015-04-09
Methods For Forming A Round Bottom Silicon Trench Recess For Semiconductor Applications App 20150031187 - Han; Joo Won ; et al.	2015-01-29
Methods for forming three dimensional NAND structures atop a substrate Grant 8,937,021 - Cho , et al. January 20, 2	2015-01-20
Methods for forming a round bottom silicon trench recess for semiconductor applications Grant 8,932,947 - Han , et al. January 13, 2	2015-01-13
Methods For Forming Three Dimensional Nand Structures Atop A Substrate App 20140377959 - CHO; HAN SOO ; et al.	2014-12-25
Self Aligned Dual Patterning Technique Enhancement With Magnetic Shielding App 20140212994 - KIM; Hun Sang ; et al.	2014-07-31
Multi-film stack etching with polymer passivation of an overlying etched layer Grant 8,747,684 - Srinivasan , et al. June 10, 2	2014-06-10
Substrate support temperature control Grant 8,596,336 - Fovell , et al. December 3, 2	2013-12-03
Methods For Etching Substrates Using Pulsed Dc Voltage App 20120088371 - RANJAN; ALOK ; et al.	2012-04-12
Multi-film Stack Etching With Polymer Passivation Of An Overlying Etched Layer App 20110045672 - Srinivasan; Sunil ; et al.	2011-02-24
Fast Substrate Support Temperature Control App 20090294101 - FOVELL; RICHARD ; et al.	2009-12-03
Etching And Passivating For High Aspect Ratio Features App 20080286978 - Chen; Rong ; et al.	2008-11-20
Encapsulation of post-etch halogenic residue App 20060032833 - Kawaguchi; Mark Naoshi ; et al.	2006-02-16
Method of releasing devices from a substrate Grant 6,905,616 - Kumar , et al. June 14, 2	2005-06-14
Method for etching high-aspect-ratio features Grant 6,897,155 - Kumar , et al. May 24, 2	2005-05-24
Method of releasing devices from a substrate App 20040173575 - Kumar, Ajay ; et al.	2004-09-09
Method of etching a trench in a silicon-on-insulator (SOI) structure Grant 6,759,340 - Nallan , et al. July 6, 2	2004-07-06
Method for laterally etching a semiconductor structure App 20040077178 - Yang, Chan-Syun ; et al.	2004-04-22
Method for etching high-aspect-ratio features App 20040033697 - Kumar, Ajay ; et al.	2004-02-19
Method of forming a capacitor using a high K dielectric material App 20030222296 - Kumar, Ajay ; et al.	2003-12-04
Method of etching a trench in a silicon-on-insulator (SOI) structure App 20030211753 - Nallan, Padmapani C. ; et al.	2003-11-13

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