Key; Kenneth Michael

Patent Applications and Registrations

Patent applications and USPTO patent grants for Key; Kenneth Michael.The latest application filed is for "architecture for a processor complex of an arrayed pipelined processing engine".

Company Profile

0.14.2

Key; Kenneth Michael - Raleigh NC

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Programmable arrayed processing engine architecture for a network switch Grant 7,895,412 - Kerr , et al. February 22, 2	2011-02-22
Architecture for a processor complex of an arrayed pipelined processing engine Grant 7,380,101 - Wright , et al. May 27, 2	2008-05-27
Processor isolation technique for integrated multi-processor systems Grant 7,185,224 - Fredenburg , et al. February 27, 2	2007-02-27
Architecture for a processor complex of an arrayed pipelined processing engine App 20050125643 - Wright, Michael L. ; et al.	2005-06-09
Electronic system modeling using actual and approximated system properties Grant 6,876,961 - Marshall , et al. April 5, 2	2005-04-05
Architecture for a processor complex of an arrayed pipelined processing engine Grant 6,836,838 - Wright , et al. December 28, 2	2004-12-28
Processor isolation method for integrated multi-processor systems Grant 6,681,341 - Fredenburg , et al. January 20, 2	2004-01-20
Programmable processing engine for efficiently processing transient data Grant 6,513,108 - Kerr , et al. January 28, 2	2003-01-28
Testing of replicated components of electronic device Grant 6,385,747 - Scott , et al. May 7, 2	2002-05-07
Pooled receive and transmit queues to access a shared bus in a multi-port switch asic Grant 6,356,548 - Nellenbach , et al. March 12, 2	2002-03-12
Synchronization and control system for an arrayed processing engine Grant 6,272,621 - Key , et al. August 7, 2	2001-08-07
Architecture for a processor complex of an arrayed pipelined processing engine App 20010000046 - Wright, Michael L. ; et al.	2001-03-15
Method and apparatus for passing data among processor complex stages of a pipelined processing engine Grant 6,195,739 - Wright , et al. February 27, 2	2001-02-27
Parallel processor with debug capability Grant 6,173,386 - Key , et al. January 9, 2	2001-01-09
Synchronization and control system for an arrayed processing engine Grant 6,119,215 - Key , et al. September 12, 2	2000-09-12
System for context switching between processing elements in a pipeline of processing elements Grant 6,101,599 - Wright , et al. August 8, 2	2000-08-08

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