loadpatents
name:-0.024366140365601
name:-0.018022060394287
name:-0.0024421215057373
Keser; Lizabeth Ann Patent Filings

Keser; Lizabeth Ann

Patent Applications and Registrations

Patent applications and USPTO patent grants for Keser; Lizabeth Ann.The latest application filed is for "redistribution layer (rdl) fan-out wafer level packaging (fowlp) structure".

Company Profile
1.17.21
  • Keser; Lizabeth Ann - San Diego CA
  • Keser; Lizabeth Ann - Chandler AZ
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
System, apparatus, and method for embedding a 3D component with an interconnect structure
Grant 10,163,687 - Rae , et al. Dec
2018-12-25
Semiconductor device comprising mold for top side and sidewall protection
Grant 10,141,202 - Alvarado , et al. Nov
2018-11-27
System, apparatus, and method for embedding a device in a faceup workpiece
Grant 9,985,010 - Rae , et al. May 29, 2
2018-05-29
Redistribution Layer (rdl) Fan-out Wafer Level Packaging (fowlp) Structure
App 20170373032 - OH; Jihoon ;   et al.
2017-12-28
Semiconductor package interconnect
Grant 9,806,052 - Keser , et al. October 31, 2
2017-10-31
Planar fan-out wafer level packaging
Grant 9,806,048 - Keser , et al. October 31, 2
2017-10-31
Planar Fan-out Wafer Level Packaging
App 20170271289 - KESER; Lizabeth Ann ;   et al.
2017-09-21
Low profile integrated circuit (IC) package comprising a plurality of dies
Grant 9,679,873 - Keser , et al. June 13, 2
2017-06-13
Package on package (POP) device comprising solder connections between integrated circuit device packages
Grant 9,601,472 - Keser , et al. March 21, 2
2017-03-21
Semiconductor Package Interconnect
App 20170077053 - KESER; Lizabeth Ann ;   et al.
2017-03-16
Low Profile Integrated Circuit (ic) Package Comprising A Plurality Of Dies
App 20160372446 - Keser; Lizabeth Ann ;   et al.
2016-12-22
System, Apparatus, And Method For Embedding A Device In A Faceup Workpiece
App 20160343635 - RAE; David Fraser ;   et al.
2016-11-24
High Aspect Ratio Interconnect For Wafer Level Package (wlp) And Integrated Circuit (ic) Package
App 20160343646 - Alvarado; Reynante Tamunan ;   et al.
2016-11-24
System, Apparatus, And Method For Embedding A 3d Component With An Interconnect Structure
App 20160343651 - RAE; David Fraser ;   et al.
2016-11-24
Package On Package (pop) Device Comprising Solder Connections Between Integrated Circuit Device Packages
App 20160315072 - Keser; Lizabeth Ann ;   et al.
2016-10-27
Crack stopping structure in wafer level packaging (WLP)
Grant 9,379,065 - Keser , et al. June 28, 2
2016-06-28
Wafer level package without sidewall cracking
Grant 9,318,405 - Xu , et al. April 19, 2
2016-04-19
Integrated device comprising wires as vias in an encapsulation layer
Grant 9,209,110 - Alvarado , et al. December 8, 2
2015-12-08
Integrated Device Comprising Wires As Vias In An Encapsulation Layer
App 20150325496 - Alvarado; Reynante Tamunan ;   et al.
2015-11-12
Wafer Level Package And Fan Out Reconstitution Process For Making The Same
App 20150318229 - XU; Jianwen ;   et al.
2015-11-05
Stacked redistribution layers on die
Grant 9,171,782 - Hau-Riege , et al. October 27, 2
2015-10-27
Method for singulating electronic components from a substrate
Grant 9,142,434 - Gao , et al. September 22, 2
2015-09-22
Via Under The Interconnect Structures For Semiconductor Devices
App 20150228594 - Alvarado; Reynante Tamunan ;   et al.
2015-08-13
Crack Stopping Structure In Wafer Level Packaging (wlp)
App 20150048517 - Keser; Lizabeth Ann ;   et al.
2015-02-19
Stacked Redistribution Layers On Die
App 20150041982 - Hau-Riege; Christine Sung-An ;   et al.
2015-02-12
Semiconductor Device Comprising Mold For Top Side And Sidewall Protection
App 20140339712 - Alvarado; Reynante Tamunan ;   et al.
2014-11-20
Method For Singulating Electronic Components From A Substrate
App 20110217814 - Gao; Wei ;   et al.
2011-09-08
Electronic Device And Method Of Packaging An Electronic Device
App 20100252919 - Xu; Jianwen ;   et al.
2010-10-07
Method For Forming A Microelectronic Assembly Including Encapsulating A Die Using A Sacrificial Layer
App 20080182363 - Amrine; Craig S. ;   et al.
2008-07-31
Methods and apparatus for thermal management in a multi-layer embedded chip structure
Grant 7,405,102 - Lee , et al. July 29, 2
2008-07-29
Methods and apparatus for thermal management in a multi-layer embedded chip structure
App 20070284711 - Lee; Tien Yu T. ;   et al.
2007-12-13
Perforated embedded plane package and method
App 20070212813 - Fay; Owen R. ;   et al.
2007-09-13
Simplification of ball attach method using super-saturated fine crystal flux
Grant 7,108,755 - Wetz , et al. September 19, 2
2006-09-19
Under bump metallurgy structural design for high reliability bumped packages
Grant 6,930,032 - Sarihan , et al. August 16, 2
2005-08-16
Simplification of ball attach method using super-saturated fine crystal flux
App 20040020562 - Wetz, Li Ann ;   et al.
2004-02-05
Under bump metallurgy structural design for high reliability bumped packages
App 20030214036 - Sarihan, Vijay ;   et al.
2003-11-20
Stress compensation composition and semiconductor component formed using the stress compensation composition
Grant 6,458,622 - Keser , et al. October 1, 2
2002-10-01

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