Kerzman; Joseph P.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kerzman; Joseph P..The latest application filed is for "phase interpolator".

Company Profile

4.15.2

Kerzman; Joseph P. - New Brighton MN
Kerzman; Joseph P. - Spring Lake Park MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Phase interpolator Grant 10,840,924 - Wurzer , et al. November 17, 2	2020-11-17
Phase Interpolator App 20190363723 - Wurzer; Steven G. ; et al.	2019-11-28
Phase interpolator Grant 10,425,090 - Wurzer , et al. Sept	2019-09-24
Phase Interpolator App 20190081632 - Wurzer; Steven G. ; et al.	2019-03-14
Phase interpolator Grant 10,153,775 - Wurzer , et al. Dec	2018-12-11
Method and apparatus for efficiently viewing a number of selected components using a database editor tool Grant 7,076,410 - Kerzman , et al. July 11, 2	2006-07-11
Method and apparatus for associating selected circuit instances and for performing a group operation thereon Grant 6,910,200 - Aubel , et al. June 21, 2	2005-06-21
Method and apparatus for using a placement tool to manipulate cell substitution lists Grant 6,701,289 - Garnett , et al. March 2, 2	2004-03-02
Method and apparatus for selecting components within a circuit design database Grant 6,684,376 - Kerzman , et al. January 27, 2	2004-01-27
Method and apparatus for selectively viewing nets within a database editor tool Grant 6,516,456 - Garnett , et al. February 4, 2	2003-02-04
Method and apparatus for distributing a clock tree within a hierarchical circuit design Grant 5,912,820 - Kerzman , et al. June 15, 1	1999-06-15
Method and apparatus for resolving conflicts between cell substitution recommendations provided by a drive strength adjust tool Grant 5,726,903 - Kerzman , et al. March 10, 1	1998-03-10
Method and apparatus for performing drive strength adjust optimization in a circuit design Grant 5,724,250 - Kerzman , et al. March 3, 1	1998-03-03
Method and apparatus for performing timing analysis on a circuit design Grant 5,719,783 - Kerzman , et al. February 17, 1	1998-02-17
Method for placing logic functions and cells in a logic design using floor planning by analogy Grant 5,696,693 - Aubel , et al. December 9, 1	1997-12-09
Address prediction for relative-to-absolute addressing Grant 5,611,065 - Alferness , et al. March 11, 1	1997-03-11
Hierarchical queuing in a system architecture for improved message passing and process synchronization Grant 5,555,396 - Alferness , et al. September 10, 1	1996-09-10

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