Kersten; Dale

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kersten; Dale.The latest application filed is for "method of forming a laminate structure having a plated through-hole using a removable cover layer".

Company Profile

6.10.14

Kersten; Dale - Ben Lomond CA
Kersten; Dale - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods of forming high aspect ratio plated through holes and high precision stub removal in a printed circuit board Grant 11,399,439 - Thomas , et al. July 26, 2	2022-07-26
Laminate structures with hole plugs and methods of forming laminate structures with hole plugs Grant 11,246,226 - Iketani , et al. February 8, 2	2022-02-08
Method Of Forming A Laminate Structure Having A Plated Through-hole Using A Removable Cover Layer App 20210014980 - Iketani; Shinichi ; et al.	2021-01-14
Simultaneous And Selective Wide Gap Partitioning Of Via Structures Using Plating Resist App 20200383204 - Iketani; Shinichi ; et al.	2020-12-03
Method of forming a laminate structure having a plated through-hole using a removable cover layer Grant 10,757,819 - Iketani , et al. A	2020-08-25
Simultaneous and selective wide gap partitioning of via structures using plating resist Grant 10,667,390 - Iketani , et al.	2020-05-26
Simultaneous and selective wide gap partitioning of via structures using plating resist Grant 10,362,687 - Iketani , et al.	2019-07-23
Laminate Structures With Hole Plugs And Methods Of Forming Laminate Structures With Hole Plugs App 20190208645 - Iketani; Shinichi ; et al.	2019-07-04
Methods Of Forming High Aspect Ratio Plated Through Holes And High Precision Stub Removal In A Printed Circuit Board App 20190159346 - THOMAS; Douglas Ward ; et al.	2019-05-23
Method for forming hole plug Grant 10,237,983 - Iketani , et al.	2019-03-19
Simultaneous And Selective Wide Gap Partitioning Of Via Structures Using Plating Resist App 20190075662 - Iketani; Shinichi ; et al.	2019-03-07
Methods of forming high aspect ratio plated through holes and high precision stub removal in a printed circuit board Grant 10,188,001 - Thomas , et al. Ja	2019-01-22
Simultaneous and selective wide gap partitioning of via structures using plating resist Grant 10,123,432 - Iketani , et al. November 6, 2	2018-11-06
Methods Of Forming Segmented Vias For Printed Circuit Boards App 20180317327 - IKETANI; Shinichi ; et al.	2018-11-01
Simultaneous And Selective Wide Gap Partitioning Of Via Structures Using Plating Resist App 20180098426 - Iketani; Shinichi ; et al.	2018-04-05
Simultaneous And Selective Wide Gap Partitioning Of Via Structures Using Plating Resist App 20180092222 - Iketani; Shinichi ; et al.	2018-03-29
Simultaneous and selective wide gap partitioning of via structures using plating resist Grant 9,781,844 - Iketani , et al. October 3, 2	2017-10-03
Simultaneous and selective wide gap partitioning of via structures using plating resist Grant 9,781,830 - Iketani , et al. October 3, 2	2017-10-03
Hole plug for thin laminate App 20160219703 - Iketani; Shinichi ; et al.	2016-07-28
Methods Of Forming High Aspect Ratio Plated Through Holes And High Precision Stub Removal In A Printed Circuit Board App 20150208514 - THOMAS; Douglas Ward ; et al.	2015-07-23
Methods Of Forming Segmented Vias For Printed Circuit Boards App 20150181724 - IKETANI; Shinichi ; et al.	2015-06-25
Method Of Forming A Laminate Structure Having A Plated Through-hole Using A Removable Cover Layer App 20150007933 - Iketani; Shinichi ; et al.	2015-01-08
Simultaneous And Selective Wide Gap Partitioning Of Via Structures Using Plating Resist App 20140262455 - Iketani; Shinichi ; et al.	2014-09-18
Simultaneous And Selective Wide Gap Partitioning Of Via Structures Using Plating Resist App 20140251663 - Iketani; Shinichi ; et al.	2014-09-11

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