Kerstan; Michael

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kerstan; Michael.The latest application filed is for "method and apparatus for trimming the working layers of a double-side grinding apparatus".

Company Profile

0.20.14

Kerstan; Michael - Burghausen N/A DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method for polishing a semiconductor wafer Grant 10,707,069 - Schwandner , et al.	2020-07-07
Carrier, method for coating a carrier, and method for the simultaneous double-side material-removing machining of semiconductor wafers Grant 9,539,695 - Pietsch , et al. January 10, 2	2017-01-10
Method and apparatus for trimming the working layers of a double-side grinding apparatus Grant 9,011,209 - Pietsch , et al. April 21, 2	2015-04-21
Method for trimming the working layers of a double-side grinding apparatus Grant 8,986,070 - Pietsch , et al. March 24, 2	2015-03-24
Insert carrier and method for the simultaneous double-side material-removing processing of semiconductor wafers Grant 8,974,267 - Pietsch , et al. March 10, 2	2015-03-10
Method for trimming the working layers of a double-side grinding apparatus Grant 8,911,281 - Pietsch , et al. December 16, 2	2014-12-16
Method And Apparatus For Trimming The Working Layers Of A Double-side Grinding Apparatus App 20140170939 - Pietsch; Georg ; et al.	2014-06-19
Method And Apparatus For Trimming The Working Layers Of A Double-side Grinding Apparatus App 20140170942 - Pietsch; Georg ; et al.	2014-06-19
Method for producing a semiconductor wafer Grant 8,685,270 - Schwandner , et al. April 1, 2	2014-04-01
Method for producing a semiconductor wafer Grant 8,529,315 - Schwandner , et al. September 10, 2	2013-09-10
Method for the simultaneous double-sided material removal processing of a plurality of semiconductor wafers Grant 8,512,099 - Kerstan , et al. August 20, 2	2013-08-20
Insert Carrier And Method For The Simultaneous Double-side Material-removing Processing Of Semiconductor Wafers App 20120190277 - Pietsch; Georg ; et al.	2012-07-26
Method for the simultaneous grinding of a plurality of semiconductor wafers Grant 8,113,913 - Pietsch , et al. February 14, 2	2012-02-14
Method And Apparatus For Trimming The Working Layers Of A Double-side Grinding Apparatus App 20120028546 - Pietsch; Georg ; et al.	2012-02-02
Method For Polishing A Semiconductor Wafer App 20110223841 - Schwandner; Juergen ; et al.	2011-09-15
Method For Producing A Semiconductor Wafer App 20110183582 - Schwandner; Juergen ; et al.	2011-07-28
Method For Producing A Semiconductor Wafer App 20110097975 - SCHWANDNER; Juergen ; et al.	2011-04-28
Semiconductor wafer, apparatus and process for producing the semiconductor wafer Grant 7,867,059 - Pietsch , et al. January 11, 2	2011-01-11
Method for the simultaneous double-side grinding of a plurality of semiconductor wafers Grant 7,815,489 - Pietsch , et al. October 19, 2	2010-10-19
Device For The Double-Sided Processing Of Flat Workpieces and Method For The Simultaneous Double-Sided Material Removal Processing Of A Plurality Of Semiconductor Wafers App 20100099337 - Kerstan; Michael ; et al.	2010-04-22
Semiconductor Wafer, Apparatus and Process For Producing The Semiconductor Wafer App 20090203297 - Pietsch; Georg ; et al.	2009-08-13
Carrier, Method For Coating A Carrier, and Method For The Simultaneous Double-Side Material-Removing Machining Of Semiconductor Wafers App 20090104852 - Pietsch; Georg ; et al.	2009-04-23
Method For The Simultaneous Grinding Of A Plurality Of Semiconductor Wafers App 20080233840 - Pietsch; Georg ; et al.	2008-09-25
Method For The Simultaneous Double-Side Grinding Of A Plurality Of Semiconductor Wafers, And Semiconductor Wafer Having Outstanding Flatness App 20080014839 - Pietsch; Georg ; et al.	2008-01-17
Semiconductor wafer with improved local flatness, and method for its production Grant 7,077,726 - Pietsch , et al. July 18, 2	2006-07-18
Semiconductor wafer, apparatus and process for producing the semiconductor wafer App 20050173377 - Pietsch, Georg ; et al.	2005-08-11
Semiconductor wafer with improved local flatness, and method for its production App 20030060050 - Pietsch, Georg J. ; et al.	2003-03-27

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.