Kerr; Darren

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kerr; Darren.The latest application filed is for "architecture for a processor complex of an arrayed pipelined processing engine".

Company Profile

0.17.3

Kerr; Darren - Palo Alto CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Programmable arrayed processing engine architecture for a network switch Grant 7,895,412 - Kerr , et al. February 22, 2	2011-02-22
Architecture for a processor complex of an arrayed pipelined processing engine Grant 7,380,101 - Wright , et al. May 27, 2	2008-05-27
Flexible, high performance support for QoS on an arbitrary number of queues Grant 7,292,578 - Kerr , et al. November 6, 2	2007-11-06
Zero overhead resource locks with attributes Grant 7,290,105 - Jeter, Jr. , et al. October 30, 2	2007-10-30
Selected register decode values for pipeline stage register addressing Grant 7,139,899 - Kerr , et al. November 21, 2	2006-11-21
Barrier synchronization mechanism for processors of a systolic array Grant 7,100,021 - Marshall , et al. August 29, 2	2006-08-29
Boundary synchronization mechanism for a processor of a systolic array Grant 6,986,022 - Marshall , et al. January 10, 2	2006-01-10
Packet striping across a parallel header processor Grant 6,965,615 - Kerr , et al. November 15, 2	2005-11-15
Tightly coupled software protocol decode with hardware data encryption Grant 6,920,562 - Kerr , et al. July 19, 2	2005-07-19
Architecture for a processor complex of an arrayed pipelined processing engine App 20050125643 - Wright, Michael L. ; et al.	2005-06-09
Architecture for a processor complex of an arrayed pipelined processing engine Grant 6,836,838 - Wright , et al. December 28, 2	2004-12-28
Sequence control mechanism for enabling out of order context processing Grant 6,804,815 - Kerr , et al. October 12, 2	2004-10-12
Selected Register Decode Values For Pipeline Stage Register Addressing App 20030159021 - KERR, DARREN ; et al.	2003-08-21
Programmable processing engine for efficiently processing transient data Grant 6,513,108 - Kerr , et al. January 28, 2	2003-01-28
Synchronization and control system for an arrayed processing engine Grant 6,272,621 - Key , et al. August 7, 2	2001-08-07
Architecture for a processor complex of an arrayed pipelined processing engine App 20010000046 - Wright, Michael L. ; et al.	2001-03-15
Method and apparatus for passing data among processor complex stages of a pipelined processing engine Grant 6,195,739 - Wright , et al. February 27, 2	2001-02-27
Parallel processor with debug capability Grant 6,173,386 - Key , et al. January 9, 2	2001-01-09
Synchronization and control system for an arrayed processing engine Grant 6,119,215 - Key , et al. September 12, 2	2000-09-12
System for context switching between processing elements in a pipeline of processing elements Grant 6,101,599 - Wright , et al. August 8, 2	2000-08-08

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