Kepler; Nicholas J.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Kepler; Nicholas J..The latest application filed is for "minimizing transistor size in integrated circuits".
- Kepler; Nicholas J. - San Jose CA
- Kepler; Nicholas J. - Saratoga CA
| Patent | Date |
|---|---|
| Minimizing transistor size in integrated circuits Grant 7,026,691 - Sander , et al. April 11, 2 | 2006-04-11 |
| Method and test structure for characterizing sidewall damage in a semiconductor device Grant 6,600,333 - Martin , et al. July 29, 2 | 2003-07-29 |
| Minimizing transistor size in integrated circuits Grant 6,287,953 - Sander , et al. September 11, 2 | 2001-09-11 |
| Method of forming a semiconductor device with metal silicide regions Grant 6,268,255 - Besser , et al. July 31, 2 | 2001-07-31 |
| Minimizing transistor size in integrated circuits Grant 6,146,954 - Klein , et al. November 14, 2 | 2000-11-14 |
| Forming local interconnects in integrated circuits Grant 6,051,881 - Klein , et al. April 18, 2 | 2000-04-18 |
| Method for self-aligning polysilicon gates with field isolation and the resultant structure Grant 6,046,088 - Klein , et al. April 4, 2 | 2000-04-04 |
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