Kepler Computing Inc.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kepler Computing Inc..The latest application filed is for "integration of ferroelectric memory devices with transistors".

Company Profile

31.82.53

Kepler Computing Inc. - San Francisco CA US

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Majority logic gate based flip-flop with non-linear polar material Grant 11,451,232 - Manipatruni , et al. September 20, 2	2022-09-20
Doped polar layers and semiconductor device incorporating same Grant 11,444,203 - Ramamoorthy , et al. September 13, 2	2022-09-13
Mobile phone with magnetic card emulation Grant 11,436,461 - Narendra , et al. September 6, 2	2022-09-06
Integration Of Ferroelectric Memory Devices With Transistors App 20220278116 - Manipatruni; Sasikanth ; et al.	2022-09-01
Ferroelectric capacitor and method of patterning such Grant 11,430,861 - Thareja , et al. August 30, 2	2022-08-30
Stacked ferroelectric non-planar capacitors in a memory bit-cell Grant 11,423,967 - Dokania , et al. August 23, 2	2022-08-23
Doped polar layers and semiconductor device incorporating same Grant 11,417,768 - Ramamoorthy , et al. August 16, 2	2022-08-16
Majority logic gate having paraelectric input capacitors and a local conditioning mechanism Grant 11,418,197 - Dokania , et al. August 16, 2	2022-08-16
Doped polar layers and semiconductor device incorporating same Grant 11,411,116 - Ramamoorthy , et al. August 9, 2	2022-08-09
Doped polar layers and semiconductor device incorporating same Grant 11,398,570 - Ramamoorthy , et al. July 26, 2	2022-07-26
2-input NAND gate with non-linear input capacitors Grant 11,394,387 - Manipatruni , et al. July 19, 2	2022-07-19
Low power ferroelectric based majority logic gate multiplier Grant 11,381,244 - Manipatruni , et al. July 5, 2	2022-07-05
Method for improving memory bandwidth through read and restore decoupling Grant 11,373,728 - Wilkerson , et al. June 28, 2	2022-06-28
Apparatus for improving memory bandwidth through read and restore decoupling Grant 11,373,727 - Wilkerson , et al. June 28, 2	2022-06-28
Majority logic gate with non-linear input capacitors and conditioning logic Grant 11,374,575 - Dokania , et al. June 28, 2	2022-06-28
Linear input and non-linear output threshold logic gate Grant 11,374,574 - Manipatruni , et al. June 28, 2	2022-06-28
Ferroelectric Based Latch App 20220200602 - Manipatruni; Sasikanth ; et al.	2022-06-23
Low Power Ferroelectric Based Majority Logic Gate Multiplier App 20220200600 - Manipatruni; Sasikanth ; et al.	2022-06-23
Majority Logic Gate Based Flip-flop With Non-linear Polar Material App 20220200601 - Manipatruni; Sasikanth ; et al.	2022-06-23
Integration Of A Ferroelectric Memory Device With A Transistor App 20220199633 - Thareja; Gaurav ; et al.	2022-06-23
Efficient method for improving memory bandwidth through read and restore decoupling using restore buffer Grant 11,366,589 - Wilkerson , et al. June 21, 2	2022-06-21
Majority Gate Based Low Power Ferroelectric Based Adder With Reset Mechanism App 20220190831 - Manipatruni; Sasikanth ; et al.	2022-06-16
Doped polar layers and semiconductor device incorporating same Grant 11,355,643 - Ramamoorthy , et al. June 7, 2	2022-06-07
Doped polar layers and semiconductor device incorporating same Grant 11,349,031 - Ramamoorthy , et al. May 31, 2	2022-05-31
Ferroelectric or paraelectric based sequential circuit Grant 11,303,280 - Mathuriya , et al. April 12, 2	2022-04-12
Apparatus and method for endurance of non-volatile memory banks via wear leveling and random swap injection Grant 11,295,796 - Wilkerson , et al. April 5, 2	2022-04-05
Low power ferroelectric based majority logic gate adder Grant 11,296,708 - Manipatruni , et al. April 5, 2	2022-04-05
Doped polar layers and semiconductor device incorporating same Grant 11,296,228 - Ramamoorthy , et al. April 5, 2	2022-04-05
Majority logic gate based XOR logic gate with non-linear input capacitors Grant 11,290,112 - Manipatruni , et al. March 29, 2	2022-03-29
Integration method of ferroelectric memory array Grant 11,289,497 - Thareja , et al. March 29, 2	2022-03-29
Doped polar layers and semiconductor device incorporating same Grant 11,289,608 - Ramamoorthy , et al. March 29, 2	2022-03-29
Majority logic gate based and-or-invert logic gate with non-linear input capacitors Grant 11,290,111 - Manipatruni , et al. March 29, 2	2022-03-29
Doped polar layers and semiconductor device incorporating same Grant 11,289,607 - Ramamoorthy , et al. March 29, 2	2022-03-29
Low power ferroelectric based majority logic gate carry propagate and serial adder Grant 11,283,453 - Manipatruni , et al. March 22, 2	2022-03-22
Majority logic gate with non-linear input capacitors Grant 11,277,137 - Manipatruni , et al. March 15, 2	2022-03-15
Doped Polar Layers And Semiconductor Device Incorporating Same App 20220077319 - Ramamoorthy; Ramesh ; et al.	2022-03-10
Artificial intelligence processor with three-dimensional stacked memory Grant 11,171,115 - Manipatruni , et al. November 9, 2	2021-11-09
Doped Polar Layers And Semiconductor Device Incorporating Same App 20210343873 - Ramamoorthy; Ramesh ; et al.	2021-11-04
Doped Polar Layers And Semiconductor Device Incorporating Same App 20210343874 - Ramamoorthy; Ramesh ; et al.	2021-11-04
Doped Polar Layers And Semiconductor Device Incorporating Same App 20210343872 - Ramamoorthy; Ramesh ; et al.	2021-11-04
Doped Polar Layers And Semiconductor Device Incorporating Same App 20210343871 - Ramamoorthy; Ramesh ; et al.	2021-11-04
Majority logic gate based sequential circuit Grant 11,165,430 - Manipatruni , et al. November 2, 2	2021-11-02
Doped polar layers and semiconductor device incorporating same Grant 11,164,976 - Ramamoorthy , et al. November 2, 2	2021-11-02
Doped Polar Layers And Semiconductor Device Incorporating Same App 20210328067 - Ramamoorthy; Ramesh ; et al.	2021-10-21
3D integrated ultra high-bandwidth multi-stacked memory Grant 11,152,343 - Dokania , et al. October 19, 2	2021-10-19
Doped Polar Layers And Semiconductor Device Incorporating Same App 20210320211 - Ramamoorthy; Ramesh ; et al.	2021-10-14
Artificial intelligence processor with three-dimensional stacked memory Grant 11,139,270 - Manipatruni , et al. October 5, 2	2021-10-05
Low Power Ferroelectric Based Majority Logic Gate Adder App 20210226636 - Manipatruni; Sasikanth ; et al.	2021-07-22
Integration Method Of Ferroelectric Memory Array App 20210202510 - Thareja; Gaurav ; et al.	2021-07-01
Linear Input And Non-linear Output Threshold Logic Gate App 20210203325 - Manipatruni; Sasikanth ; et al.	2021-07-01
Ferroelectric Capacitor And Method Of Patterning Such App 20210202689 - Thareja; Gaurav ; et al.	2021-07-01
Method For Using And Forming Low Power Ferroelectric Based Majority Logic Gate Adder App 20210203326 - Manipatruni; Sasikanth ; et al.	2021-07-01
Pillar Capacitor And Method Of Fabricating Such App 20210202507 - Thareja; Gaurav ; et al.	2021-07-01
Ferroelectric Capacitor Integrated With Logic App 20210202690 - Thareja; Gaurav ; et al.	2021-07-01
Low Power Ferroelectric Based Majority Logic Gate Adder App 20210203324 - Manipatruni; Sasikanth ; et al.	2021-07-01
3D integrated ultra high-bandwidth memory Grant 11,043,472 - Dokania , et al. June 22, 2	2021-06-22
Linear input and non-linear output threshold logic gate Grant 11,025,254 - Manipatruni , et al. June 1, 2	2021-06-01
Linear input and non-linear output majority logic gate Grant 11,018,672 - Manipatruni , et al. May 25, 2	2021-05-25
Linear input and non-linear output majority logic gate with and/or function Grant 11,012,076 - Manipatruni , et al. May 18, 2	2021-05-18
High-density low voltage non-volatile differential memory bit-cell with shared plate-line Grant 10,998,025 - Manipatruni , et al. May 4, 2	2021-05-04
Majority logic gate fabrication Grant 10,951,213 - Manipatruni , et al. March 16, 2	2021-03-16
Low power ferroelectric based majority logic gate adder Grant 10,944,404 - Manipatruni , et al. March 9, 2	2021-03-09
High-density low voltage non-volatile differential memory bit-cell with shared plate line Grant 10,847,201 - Manipatruni , et al. November 24, 2	2020-11-24
Doped Polar Layers And Semiconductor Device Incorporating Same App 20200321344 - Ramamoorthy; Ramesh ; et al.	2020-10-08
Doped Polar Layers And Semiconductor Device Incorporating Same App 20200321472 - Ramamoorthy; Ramesh ; et al.	2020-10-08
Doped Polar Layers And Semiconductor Device Incorporating Same App 20200321473 - Ramamoorthy; Ramesh ; et al.	2020-10-08
Doped Polar Layers And Semiconductor Device Incorporating Same App 20200321474 - Ramamoorthy; Ramesh ; et al.	2020-10-08
Artificial Intelligence Processor With Three-dimensional Stacked Memory App 20200303344 - MANIPATRUNI; Sasikanth ; et al.	2020-09-24
Artificial Intelligence Processor With Three-dimensional Stacked Memory App 20200303343 - MANIPATRUNI; Sasikanth ; et al.	2020-09-24
High-density Low Voltage Non-volatile Differential Memory Bit-cell With Shared Plate-line App 20200273514 - Manipatruni; Sasikanth ; et al.	2020-08-27
High-density Low Voltage Non-volatile Memory With Unidirectional Plate-line And Bit-line And Pillar Capacitor App 20200273864 - Manipatruni; Sasikanth ; et al.	2020-08-27
High-density Low Voltage Non-volatile Differential Memory Bit-cell With Shared Plate-line App 20200273865 - Manipatruni; Sasikanth ; et al.	2020-08-27
High-density Low Voltage Non-volatile Memory With Unidirectional Plate-line And Bit-line And Pillar Capacitor App 20200273866 - Manipatruni; Sasikanth ; et al.	2020-08-27
High-density Low Voltage Non-volatile Memory With Unidirectional Plate-line And Bit-line And Pillar Capacitor App 20200273867 - Manipatruni; Sasikanth ; et al.	2020-08-27