Kemerer; Douglas W.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Kemerer; Douglas W..The latest application filed is for "identifying parasitic diode(s) in an integrated circuit physical design".

Company Profile

0.20.16

Kemerer; Douglas W. - Essex Junction VT
Kemerer, Douglas W. - Essex Center VT
Kemerer; Douglas W. - Beacon NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Identifying parasitic diode(s) in an integrated circuit physical design Grant 8,756,554 - Kemerer , et al. June 17, 2	2014-06-17
Identifying Parasitic Diode(s) In An Integrated Circuit Physical Design App 20130067425 - Kemerer; Douglas W. ; et al.	2013-03-14
Identifying parasitic diode(s) in an integrated circuit physical design Grant 8,191,030 - Kemerer , et al. May 29, 2	2012-05-29
Intersect area based ground rule for semiconductor design Grant 7,941,780 - Avanessian , et al. May 10, 2	2011-05-10
Mechanism for detection and compensation of NBTI induced threshold degradation Grant 7,849,426 - Goodnow , et al. December 7, 2	2010-12-07
Methods and circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications Grant 7,696,811 - Barrows , et al. April 13, 2	2010-04-13
Methods to reduce threshold voltage tolerance and skew in multi-threshold voltage applications Grant 7,671,666 - Barrows , et al. March 2, 2	2010-03-02
Programmable on-chip sense line Grant 7,619,398 - Barrows , et al. November 17, 2	2009-11-17
Intersect Area Based Ground Rule For Semiconductor Design App 20090265673 - Avanessian; Albrik ; et al.	2009-10-22
Identifying Parasitic Diode(s) In An Integrated Circuit Physical Design App 20090150842 - Kemerer; Douglas W. ; et al.	2009-06-11
Mechanism For Detection And Compensation Of Nbti Induced Threshold Degradation App 20090113358 - Goodnow; Kenneth J. ; et al.	2009-04-30
Mechanism for detection and compensation of NBTI induced threshold degradation Grant 7,504,847 - Goodnow , et al. March 17, 2	2009-03-17
Identifying parasitic diode(s) in an integrated circuit physical design Grant 7,490,303 - Kemerer , et al. February 10, 2	2009-02-10
Circuits to reduce threshold voltage tolerance and skew in multi-threshold voltage applications Grant 7,459,958 - Barrows , et al. December 2, 2	2008-12-02
Methods To Reduce Threshold Voltage Tolerance And Skew In Multi-threshold Voltage Applications App 20080265983 - Barrows; Corey Kenneth ; et al.	2008-10-30
Methods And Circuits To Reduce Threshold Voltage Tolerance And Skew In Multi-threshold Voltage Applications App 20080246533 - Barrows; Corey Kenneth ; et al.	2008-10-09
Programmable On-chip Sense Line App 20080211472 - Barrows; Corey K. ; et al.	2008-09-04
Programmable on-chip sense line Grant 7,397,228 - Barrows , et al. July 8, 2	2008-07-08
Methods And Circuits To Reduce Threshold Voltage Tolerance and Skew In Multi-Threshold Voltage Applications App 20080122524 - Barrows; Corey Kenneth ; et al.	2008-05-29
Mechanism For Detection And Compensation Of NBTI Induced Threshold Degradation App 20080094092 - Goodnow; Kenneth J ; et al.	2008-04-24
Methods And Circuits To Reduce Threshold Voltage Tolerance And Skew In Multi-threshold Voltage Applications App 20080086706 - Barrows; Corey Kenneth ; et al.	2008-04-10
Contact Via Scheme With Staggered Vias App 20070176295 - Chinthakindi; Anil K. ; et al.	2007-08-02
Programmable On-chip Sense Line App 20070162770 - Barrows; Corey K. ; et al.	2007-07-12
Integrated circuit chip having a ringed wiring layer interposed between a contact layer and a wiring grid Grant 7,146,596 - Bednar , et al. December 5, 2	2006-12-05
Method and system for improving integrated circuit manufacturing productivity Grant 7,076,749 - Kemerer , et al. July 11, 2	2006-07-11
Method And System For Improving Integrated Circuit Manufacturing Productivity App 20050278663 - Kemerer, Douglas W. ; et al.	2005-12-15
Integrated Circuit Chip Having A Ringed Wiring Layer Interposed Between A Contact Layer And A Wiring Grid App 20050050505 - Bednar, Thomas R. ; et al.	2005-03-03
Shared Ground Sram Cell App 20020101759 - Jasinski, Eric ; et al.	2002-08-01
Shared ground SRAM cell Grant 6,426,890 - Jasinski , et al. July 30, 2	2002-07-30
Method of combining gate array and standard cell circuits on a common semiconductor chip Grant 5,369,595 - Gould , et al. November 29, 1	1994-11-29
Method of combining gate array and standard cell circuits on a common semiconductor chip Grant 5,051,917 - Gould , et al. September 24, 1	1991-09-24
Method of combining gate array and standard cell circuits on a common semiconductor chip Grant 4,786,613 - Gould , et al. November 22, 1	1988-11-22
Timed True And Complement Generator Grant 3,764,823 - Donofrio , et al. October 9, 1	1973-10-09
Bipolar Capacitor Driver Grant 3,656,004 - Kemerer , et al. April 11, 1	1972-04-11

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